How to manage reset signal for VHDL test benches?

Question

I have a very simple vhdl testbench that should run. My components all have a reset signal, so that registers are set to 0 and other components correctly initialized... but... if I create a common signal for resetting all component only during the first clock cycle, how can I tell to that signal to go down after the first clock cycle and never get up again????

I know it is a stupid problem but, how would you do???????? Thank you.

+1 for even knowing what VHDL means :-) – DigitalRoss Jan 11 '11 at 17:15 — DigitalRoss, Jan 11 '11 at 17:15

score 6 · Accepted Answer · answered Jan 10 '11 at 20:22

6

reset <= '1', '0' after 10 ns;

answered Jan 10 '11 at 20:22

DigitalRoss

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i'll try in few minutes... :) – Andry Jan 10 '11 at 20:27
OK in more than few minutes... gotta dine :) – Andry Jan 10 '11 at 21:00

How to manage reset signal for VHDL test benches?

1 Answers1