Questions tagged [mmu]

For programming the MMU hardware to implement paging or virtual addressing. Please give details of the MMU hardware. Use the tags 'paging' or 'virtual-memory' for use of an MMU as opposed to hardware programming.

Please provide some details of the particular MMU in questions.

The Memory Management Unit is the part of a processor responsible for translating virtual addresses to physical addresses. The MMU makes a number of features that are taken for granted on modern desktop OSes such as process separation and virtualization possible.

An MMU is often absent from deeply embedded systems and may not be used due to resource constraints as well as real time considerations. Some CPUs provide alternatives that allow a data cache to be used.Ref: ARM MPU

Related:

  • ; a cache of mmu table values.
  • - caches interact with the MMU depending on types (VIVT, PIPT, etc)
  • - issues related using the MMU to 'swap' memory to disk.
  • - issues with using virtual memory.
  • - some systems use the MMU to implement virtualization (especially without virtualization extensions in the CPU) and others MMUs provide assistance for the hypervisor.
262 questions
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Usage of PLD instruction

I have some doubts regarding the usage of PLD instruction in ARM cortex A8. As I am using the instruction inside loop, there is a possibility of out of bound memory access. My doubt is that whether that would cause a segmentation fault or not. I…
Rugger
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How does ARM Linux emulate the dirty, accessed, and file bits of a PTE?

As per pgtable-2-level.h, ARM Linux has two version of PTE; The Linux PTE and H/W PTE. Linux PTE are stored on below a offset of 1024 bytes. When handling page fault in handle_pte_fault various function like pte_file, pte_mkdirty, pte_mkyoung, get…
AnshuMan Gupta
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Use ARM TrustZone to prevent access to memory region from Non-Secure world

Context I want to have a rich GNU/Linux OS running in the Normal world and a small OS with an integrated Monitor running in the Secure world. Requirement We have to absolutely avoid the Normal world to access the Secure world memory…
cid
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linkscript - different link address and load address

I'm wring a toy OS for my raspberry pi and trying to setup the MMU. I want to split the virtual memory between 3G:1G, so I think my code should be linked at 0xC0008000, while loaded to 0x8000 on execution. (The 0x8000 is the address the current…
jsz
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What enforces memory protection in an OS?

In general, I know that a process can't write to a memory (in its addresses space) that has a protection that doesn't allow writing. But what checks whether the process can do this? Does any assembly instruction goes through the operating system?…
Tomer
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Enabling the ARMv7 VMSA memory management unit?

So, basically, I want to enable the memory management unit on an ARMv7 core. The actual procedure is pretty much trivial. I just need to load the address of the translation table into TTBR0 and enable the MMU using the control register. /* enable…
Kristina
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Dumping page table entries of a process in Linux

I was wondering if there is any utility/code in Linux (x86-64) that could dump each page table entries for a given process's (user) address space? Thanks
Arka
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How MTRR registers implemented?

x86/x86-64 exposes MTRR (Memory-type-range-register) that can be useful to designate different portions of physical address space for different usages (e.g., Cacheable, Unchangeable, Writecombining, etc.). My question is is anybody knows how these…
Arka
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Call graph for handling TLB misses in linux kernel

I am trying to understand how the linux kernel handles TLB misses. Specifically, I know that the page table walk happens in follow_page in mm/memory.c but how is follow_page called when a TLB miss occurs. How is the return value (struct page) of…
Bhushan
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Dynamic allocation in uClinux

I'm new to embedded development, and the big differences I see between traditional Linux and uClinux is that uClinux lacks the MMU. From this article: Without VM, each process must be located at a place in memory where it can be run. In the…
Chris Tonkinson
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ARM MMU operation in various operating modes

I will put my understandings related to the topic before i ask my question, Linux Kernel mode corresponds to ARM supervisor mode. Linux User mode corresponds to ARM User Mode. In Kernel Mode (MMU enabled) , Linux uses relative address instead of…
Prabagaran
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Accessing a variable that crosses a MMU page boundary

I am learning X64 assembly language under Windows and MASM64 from the latest edition of the book "The art of 64 bit assembly language". I have a question regarding that quote from the book: You do have to worry about MMU page organization in memory…
Danny Cohen
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How to understand the ARMv8 AArch64 MMU table descriptor format in the diagram?

The diagram below is taken from ARMv8-A Programmer's Guide: I am a bit confused by the highlighted entry type. Let me state my current understanding first (suppose the scenario of a stage 1 translation in EL3 with granule size 4KB). In the first…
bruin
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Dump the contents of TLB buffer of x86 CPU

Is it possible to get list of translations (from virtual pages into physical pages) from TLB (Translation lookaside buffer, this is a special cache in the CPU). I mean modern x86 or x86_64; and I want to do it in programmatic way, not by using JTAG…
osgx
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OS response to page fault

When a page fault occurs the MMU raises and exception (interrupt). The OS stops the current processes and addresses this raised interrupt. 1) Does this mean that (for 68K architecture where there are 7 interrupt lines with 7th being un-maskable)…
rrazd
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