Questions tagged [mmu]

For programming the MMU hardware to implement paging or virtual addressing. Please give details of the MMU hardware. Use the tags 'paging' or 'virtual-memory' for use of an MMU as opposed to hardware programming.

Please provide some details of the particular MMU in questions.

The Memory Management Unit is the part of a processor responsible for translating virtual addresses to physical addresses. The MMU makes a number of features that are taken for granted on modern desktop OSes such as process separation and virtualization possible.

An MMU is often absent from deeply embedded systems and may not be used due to resource constraints as well as real time considerations. Some CPUs provide alternatives that allow a data cache to be used.Ref: ARM MPU

Related:

  • ; a cache of mmu table values.
  • - caches interact with the MMU depending on types (VIVT, PIPT, etc)
  • - issues related using the MMU to 'swap' memory to disk.
  • - issues with using virtual memory.
  • - some systems use the MMU to implement virtualization (especially without virtualization extensions in the CPU) and others MMUs provide assistance for the hypervisor.
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Parallel lookup in L1 / L2 / LLC / DRAM?

It's a weird question, but maybe someone here knows: Referring to Intel/AMD up-to-date processors, does the CPU lookup the caches and DRAM simultaneously? It might be a good way to save cycles (but is probably more power consuming). Any answer…
Simple.guy
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Mapping of Kernel Virtual address directly

I have read that if Linux kernel virtual address is between 0xC0000000 and (0xC0000000 + 896MB). The mapping is direct to the physical address. That is if RAM is at 0x80000000. Which is mapped directly to 0xC0000000. How is this achieved in Linux.…
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Changing kernel page permission for allowing user access

In x86 or x64 Linux, I am trying to make a kernel module that changes specific kernel page permission to allow user application accessing that memory. For example, if there is a readable kernel page at 0xC0001000(say it's 3:1 split), I want to…
daehee
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Redirecting DMA memory access

I'm wondering if it is possible to redirect memory reading requests of a DMA device to another address on the OS level without the DMA device being noticed. Let's say my PCIe card can access all the memory on my PC by directly reading the physical…
user2212190
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How to write a test that checks TLB locking and invalidation?

I am trying to validate a software MMU. In the testcase which I got, I need to check "TLB locking and invalidation". I ran a test and checked for the TLB miss, but I was not able to understand what exactly TLB locking and invalidation mean.
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How to read kernel page table?

Linux separates virtual memory space into two parts: 0x00000000 ~ 0xBFFFFFFF and 0xC0000000 ~ 0xFFFFFFFF. As I read, all the processes share the same kernel virtual space 0xC0000000 ~ 0xFFFFFFFF. I am trying to lock one TLB for system call on ARM…
beikesea
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SMP boot of ARM Cortex A9 sequence with MMU/cache enabled

I am trying to do SMP boot in U-boot on Dual core ARM Cortex A9 system with MMU/Cache enabled. I needed the sequence of initializations. How should be the sequence of the following things happen. In what order? MMU page table setup Set SMP bit…
prasanna
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Memory - Paging and TLB

I have question to the following task. Consider an IA-32 system where the MMU supports a two level page table. The second level contains 1024 page table entries mapping to 4 KB page frames. Each page table entry (both levels) has a size of 4 bytes.…
user2965601
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Do we require MMU when virtual address space is equal to physical address space?

The MMU is used to translate virtual address to physical address for a running process with the help of page table corresponding to that process. Lets take a scenario when the virtual address space is equal to physical address space. Do we really…
coder
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ARM bare-metal with MMU: write to non-cachable,non-bufferable mapped area fail

I am ARM Cortex A9 CPU with 2 cores. But I just use 1 core and the other is just in a busy loop. I setup the MMU table using section (1MB per entry) like this: 0x00000000-0x14ffffff => 0x00000000-0x14ffffff (non-cachable,…
sing lam
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is it possible that MMU uses more than one paging logic?

is MMU's page table walking logic fixed? or is it configurable by kernel? I though MMU's logic is always fixed but it seems to be the page table structure's are different per OS... or when I add more physical memory cards... some advice would be…
daehee
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How pkmap_page_table is used on kmap?

pkmap_page_table has a pointer of page table for kmap when kernel starts. For example, PKMAP_BASE is 0xFFE00000 and FIXADDR_START is 0xFFF00000, if kernel tries to use the high memory, TTB0's PTE should be set to 0xFFE00000 ~ 0xFFF00000 for virtual…
spring79y
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What Virtual TLB?

Does anybody knows what does it mean by Virtual TLB, and what is the difference between this VTLB and the normal TLB .. I can't find a clear answer on Google?
Abdel Hegazi
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How to debug Linux kernel Boot process after __turn_mmu_on stage?

I am trying to Boot Android 4.0.1 (Ice Cream Sandwich), based on Linux kernel 3.0.1 on a custom hardware. I am able to debug the Linux Kernel 3.0.1 boot process till __enable_mmu function defined in head.S, using serial port. But as soon as…
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How to repair segmentation fault?

I need to read the Asynchronous External Memory Interface (AEMIF) using a TMS320DM368 in an embedded linux environment on custom HW. I don't actually have the hardware yet so I am testing the vala code (below) on a Leopardboard 368. The 1st AEMIF…
jacknad
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