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Questions tagged [mmu]

For programming the MMU hardware to implement paging or virtual addressing. Please give details of the MMU hardware. Use the tags 'paging' or 'virtual-memory' for use of an MMU as opposed to hardware programming.

Please provide some details of the particular MMU in questions.

The Memory Management Unit is the part of a processor responsible for translating virtual addresses to physical addresses. The MMU makes a number of features that are taken for granted on modern desktop OSes such as process separation and virtualization possible.

An MMU is often absent from deeply embedded systems and may not be used due to resource constraints as well as real time considerations. Some CPUs provide alternatives that allow a data cache to be used.Ref: ARM MPU

Related:

  • ; a cache of mmu table values.
  • - caches interact with the MMU depending on types (VIVT, PIPT, etc)
  • - issues related using the MMU to 'swap' memory to disk.
  • - issues with using virtual memory.
  • - some systems use the MMU to implement virtualization (especially without virtualization extensions in the CPU) and others MMUs provide assistance for the hypervisor.
262 questions
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How many memory pages do C compilers on desktop OSes use to detect stack overflows?

This question is related to but different from this one about variable length arrays in C99. The answers point out that one danger with allocating variable length arrays (or just large arrays of a fixed size) in the stack is that the allocation may…
Pascal Cuoq
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VIPT Cache: Connection between TLB & Cache?

I just want to clarify the concept and could find detail enough answers which can throw some light upon how everything actually works out in the hardware. Please provide any relevant details. In case of VIPT caches, the memory request is sent in…
Uchia Itachi
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Domain in arm architecture means what

When I debug MMU in Cortex-A9 MPCore, I always see Domain Access Control Register, but, what does domain means ? up to 16 domains ? Anyone can give me a link to explain this ?
kavin zhuang
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Disable write protection for memory pages in ARM

I've researched on the topic for disabling of write protection on kernel text on linux, and I can only find solutions for x86 linux, which is temporarily clearing bit 16 of the cr0 register, write to the memory, and then setting bit 16 of the cr0…
csharpnewbie
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How do modern cpus handle crosspage unaligned access?

I'm trying to understand how unaligned memory access (UMA) works on modern processors (namely x86-64 and ARM architectures). I get that I might run into problems with UMA ranging from performance degradation till CPU fault. And I read about…
Ivan Dives
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What is a PMM arena in the context of MMU in a kernel (zircon/fuchsia)

I'm trying to understand how the Zircon's (Fuchsia OS kernel) allocs page in ARM64, so I found mmu.cpp https://fuchsia.googlesource.com/fuchsia/+/4277d3203daa0fc5e4dd1625cf96891dd9882f44/zircon/kernel/arch/arm64/mmu.cc#328 But it simply does: if…
Paprika
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Accessing two discontinuous memory blocks as a single continuous block, in C?

In Linux user space: suppose that I allocated a 3MiB continuous memory ABC, where A, B and C are 1MiB each. Is there a way to access AC as a single continuous 2MiB memory somehow (a kind of user space MMU)? Background: my scenario is to model an…
bruin
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how is CPU physical address space mapped to physical DRAM?

In a systems memory map (also called cpu memory map) the address ranges are allocated for RAM memory ranges, MMIO for PCI devices etc. Lets take an example where address ranges for RAM is started from address 0 to upto 512MB which includes DOS…
v123
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Why does access to an unmapped location not generate a hardware exception (Microblaze)

I want to write my code that will handle TLB misses on the Microblaze and through that, of course, the page tables etc. This is all being done on OVPsim. As I am learning as I go I wrote this little piece of assembly to reference an unmapped…
adrianmcmenamin
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How does Linux support more than 512GB of virtual address range in x86-64?

The user virtual address space for x86-64 with Linux is 47 bit long. Which essentially means that Linux can map a process with around ~128 TB virtual address range. However, what confuses me that x86-64 architecture supports ISA defined 4-level…
Arka
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How fast is mprotect

My question is how fast is mprotect. What will be the difference between mprotecting say 1 MB of contiguous memory as compared to 1 GB of contiguous memory? Of course I can measure the time, but I want to know what goes under the hood.
MetallicPriest
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AMD: performance counter for cycles on TLB miss

I'm looking for AMD specific performance counters which count cycles consumed by page walks when TLB misses occur. I know Intel has such metrics available. But do such exist on AMD? I looked in…
Mark
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Why does the OS need a page table if the MMU already has one?

I'm confused about where the line between OS and MMU for virtual memory management is drawn. If the MMU is responsible for translating virtual addresses to physical addresses and has an internal page table, why does the OS need to have a page table…
user12246702
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When accessing memory, will the page table accessed/dirty bit be set under a cache hit situation?

As far as I know, a memory access of CPU involves CPU cache and MMU. CPU will try to find its target in cache and if a cache miss happens, CPU will turn to MMU. During accessing by MMU, the accessed/dirty bit of correspondent page table entry will…
黄海鑫
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What is PDE cache?

I have the following specifications of an ARM based SoC: L1 Data cache = 32 KB, 64 B/line, 2-WAY, LRU L2 Cache = 1 MB, 64 B/line, 16-WAY L1 Data TLB (for loads): 32 entries, fully associative L2 Data TLB: 512 entries, 4-WAY PDE Cache: 16 entries…
Nikolai
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