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I am trying to do SMP boot in U-boot on Dual core ARM Cortex A9 system with MMU/Cache enabled. I needed the sequence of initializations. How should be the sequence of the following things happen. In what order?

  • MMU page table setup
  • Set SMP bit (core 0 and core 1)
  • invalidate cache (inner cache)
  • flushing of cache (inner and what about outer)
  • When L2 cache must be enabled?
  • When SCU must be enabled? Before SMP bit or after?

It would be a great help, if someone can list down the sequence of operations.

Thanks in advance

artless noise
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prasanna
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1 Answers1

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This is the sequence which i am currently following without any issues (like earlier there were asynchronous data aborts) But my main function isn't working, hence debugging on it.

Please review and suggest, if stil any order or anything missing.

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prasanna
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