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I have no idea about SB_RAM2048x2 memory Usage for iCE40 Devices. I find iceimage.hex mecrisp-ice 0.8 , a memory initialization file ,is being loaded into ram.v .and ram.v is being used in other verilog file. I want to use the bram instead of this ram.v so that i can use bram in zynq fpga(zybo board).I am little doubtful , is it possible to directly use SB_RAM2048x2 (mentioned in ram.v) in zynq fpga(zybo)? or is it only for iCE40 devices.

shrikant Charthal
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  • you may find a python file if u open the mecrisp-ice 0.8 folder which load the icecream.hex file in the memory. by running the python file would let u generate ram.v . – shrikant Charthal Oct 18 '19 at 18:15

1 Answers1

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SB_RAM2048x2 is an iCE40 specific primitive, it will not work on a Zynq.

You most likely want to infer memory using a Verilog array, for example

reg [1:0] mem[0:2047];
always @(posedge clk) begin
    if (wen) mem[waddr] <= wdata;
    rdata <= mem[raddr];
end

This will then work on any FPGA family.

gatecat
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  • basically , I have a memory intialization file named abc.hex. how can i load the memory file into the defined verilog array? – shrikant Charthal Oct 28 '19 at 20:31
  • will it be synthesizable ? i want to load my instruction data into a memory and run it on zynq fpga with a processor. what do you suggest? – shrikant Charthal Oct 30 '19 at 22:19
  • It's synthesisable but remember that the file is read by the synthesiser at synthesis time, then effectively baked in to the bitstream. If you want to dynamically load memory from the ARM core of the Zynq, you'll need to implement an AXI slave port to your memory – gatecat Oct 30 '19 at 22:47
  • i am sorry but i could not understand i have inferred memory reg [7:0] mem[0:4095]; always @(posedge clk) begin if (wen) mem[waddr] <= wdata; rdata <= mem[raddr]; end but how can i read my .hex file into this memory. i am using vivado. i want my .hex file into the above inferred memory. – shrikant Charthal Feb 06 '20 at 19:20