viewing waveform using scansion

Question

NOTE: if there is a better place for me to ask this, please let me know! I've googled extensively and cannot find an answer

I'm trying to view the output of a simple counter/sin LUT using the waveform viewer scansion. I am using icarus verilog to compile. So far, I've run iverilog -o sinGen_TB sinGenerator_TB on the command line, then vvp sinGen_TB

I'm getting an error that says "The document “sinGen_TB” could not be opened. Scansion cannot open files of this type."

Alternatively, when I save the file as sinGen_TB.vvp or sinGen_TB.vcd, I get "The document “sinGen_TB.vvp” could not be opened. Scansion cannot open files in the “Document” format."

What does this mean, and what can I do that will allow me to view this waveform?

Here is the code I'm compiling, if the module I'm instantiating is also needed let me know:

`include "sinGenerator"

module sinGenerator_TB();
reg clk, rst;
reg [0:3]M;
wire [16:0]data_out;

//instantiate the unit under test
sin_LUT UUT(
  .clk(clk),
  .rst(rst),
  .M(M),
  .data_out(data_out)
  );

//initialize clock
always begin
#5 clk = ~clk;
end

//initialize variables
initial begin
rst = 1;
M = 1;
#20 rst = 0;
#200 M = 2;
#200 M = 4'b0100;
#200 $stop;
end

endmodule

Rahul Menon · Answer 1 · 2016-07-12T01:26:48.357

iverilog -o sinGen_TB sinGenerator_TB only generates the final executable sinGen_TB .

use man iverilog to get more information regarding how to run the Iicarus simulator.

The executable needs to be run -vvp sinGen_TB . This will run the simulation and will produce an output file that can be opened by the waveform viewer.

[ I guess ./sinGen_TB also runs the simulation ]

You also need to add the code below to dump the waveform.

initial
 begin
    $dumpfile("sinGen_TB.vcd"); //file name 
    $dumpvars(0,sinGenerator_TB); // module name 
 end

Greg · Accepted Answer · 2017-12-18T20:06:23.810

Verilog files typically uses .v as the file extension; SystemVerilog uses .sv. Please use the file extension. It helps the simulator know what language you are trying to compile (all modern Verilog simulators are SystemVerilog simulators with backward compatibility). Plus text editors, such as vim and emacs, use the file extension to decide how to do syntax highlighting/formatting.

The simulator needs to generate the .vcd file. Scansion is just a tool to view the waveform. It has nothing to do with generating the waveform and appears to have nothing to do with the question.

For the simulator to know to where to create the VCD file it needs $dumpfile; to know what signals to put in the VCD file it needs $dumpvars. Read IEEE Std 1800-2012 § 21.7 Value change dump (VCD) files

For example if you want to dump everything and put it in dump.vcd, then add this to your test bench:

initial begin
  $dumpfile("dump.vcd");
  $dumpvars;
end

viewing waveform using scansion

2 Answers2