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I can't find an example in doc to convert a VHDL code to Verilog with icarus. I found how to do verilog to VHDL here. I tried to modify the command to do VHDL convertion on this code :

$ iverilog -tvlog95 -o button_deb.v button_deb.vhdl 
button_deb.vhdl:3: syntax error
I give up.

But I've got a syntax error. Is my VHDL code is wrong ? Or is it iverilog command that is wrong ?

FabienM
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2 Answers2

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There's no Verilog target, so you can't generate Verilog output, and VHDL compilation is still experimental anyway. You could ask on the mailing list to make sure there's nothing under the hood which could help. VHDL to Verilog conversion is only possible in relatively simple cases (synthesisable code should be Ok), so you may have to do it manually anyway.

EML
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It seems that some support has arrived in the meantime (mainly using -g2005-sv, -g2009, or -g2012 switch) . Try this:

iverilog -g2012 -tvlog95 -o button_deb.v button_deb.vhd

If you pay closer attention to the output you'll see that in this way you'll loose the two generic at the entity interface. Using vhdlpp directly could be useful:

/path/to/vhdlpp button_deb.vhd > button_deb.v
Claudio
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