HDL is a Hardware Description Language, a language used to design chips. The two major ones are Verilog and VHDL.
Taken from G.J. Lipovsky, "Hardware Description Languages: Voices from the Tower of Babel", Computer, Vol. 10, No. 6, June 1977, pp. 14-17. Paper available here.
A hardware description language can be used to describe the logic gates, the sequential machines, and the functional modules, along with their interconnection and their control, in a digital system. In a general sense, Boolean equations, logic diagrams, programrning languages, and Petri nets are hardware description languages: they can be used to describe some aspect of hardware and they have definable syntax and semantics. Specifically, what is more commonly referred to as a hardware description language is a variation of a programming language tuned to the overall needs of describing hardware.
Adapted from Hardware Description Language tutorial with very few modifications:
Hardware description language (HDL) is a specialized computer language used to program electronic and digital logic circuits. The structure, operation and design of the circuits are programmable using HDL. HDL includes a textual description consisting of operators, expressions, statements, inputs and outputs. Instead of generating a computer executable file, the HDL compilers provide a gate map. The gate map obtained is then downloaded to the programming device to check the operations of the desired circuit. The language helps to describe any digital circuit in the form of structural, behavioral and gate level and it is found to be an excellent programming language for FPGAs, CPLDs and ASICs.
The three common HDLs are Verilog, VHDL, and SystemC. Of these, SystemC is the newest. The HDLs will allow fast design and better verification. In most of the industries, Verilog and VHDL are common. Verilog, one of the main Hardware Description Language standardized as IEEE 1364 is used for designing all types of circuits. It consists of modules and the language allows Behavioral, Dataflow and Structural Description. VHDL (Very High Speed Integrated Circuit Hardware Description Language) is standardized by IEEE 1164. The design is composed of entities consisting of multiple architectures. SystemC is a language that consist a set of C++ classes and macros. It allows electronic system level and transaction modeling.
Need for HDLs
The Moore’s Law in the year 1970 has brought a drastic change in the field of IC technology. This change has made the developers to bring out complex digital and electronic circuits. But the problem was the absence of a better programming language allowing hardware and software codesign. Complex digital circuit designs require more time for development, synthesis, simulation and debugging. The arrival of HDLs has helped to solve this problem by allowing each module to be worked by a separate team.
All the goals like power, throughput, latency (delay), test coverage, functionality and area consumption required for a design can be known by using HDL. As a result, the designer can make the necessary engineering tradeoffs and can develop the design in a better and efficient way. Simple syntax, expressions, statements, concurrent and sequential programming is also necessary while describing the electronics circuits. All these features can be obtained by using a hardware description language. Now while comparing HDL and C languages, the major difference is that HDL provides the timing information of a design.
Benefits of HDL
The major benefit of the language is fast design and better verification. The Top-down design and hierarchical design method allows the design time; design cost and design errors to be reduced. Another major advantage is related to complex designs, which can be managed and verified easily. HDL provides the timing information and allows the design to be described in gate level and register transfer level. Reusability of resources is one of the other advantage.
