There are a couple of things that need to be addressed here.
Firstly, you need an entity statement:
entity proj is
port(
i_clock : in std_logic
);
end proj;
This declares what signals are inputs and outputs for your entity. In this case, it's just a clock. You can add rownum and rowcount inputs and outputs too as needed.
Your function name shouldn't be in inverted commas, and overloading an existing operator isn't a good idea either.
function rol_custom (a: std_logic_vector; n : natural)
return std_logic_vector is
begin
return std_logic_vector(unsigned(a) rol n);
end function;
Here's the synthesizable code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity proj is
port(
i_clock : in std_logic
);
end proj;
architecture main of proj is
function rol_custom (a: std_logic_vector; n : natural)
return std_logic_vector is
begin
return std_logic_vector(unsigned(a) rol n);
end function;
signal rownum : std_logic_vector(2 downto 0);
signal rowcount : std_logic_vector(2 downto 0);
begin
process begin
wait until rising_edge(i_clock);
rownum<=rol_custom(rowcount,1);
end process;
end architecture main;
However, even though this now should synthesize, the results won't make any sense, because rowcount has not been given a value. In order to define it, you might want to add a process which drives the signal based on certain criteria (a counter?) or add it as an input in the entity definition.
