0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Lab3_Adder1 is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end Lab3_Adder1;

architecture Behavioral of Lab3_Adder1 is

    SIGNAL c : STD_LOGIC_VECTOR (4 DOWNTO 0);

begin
    c(0) <= cin;
    s <= a XOR b XOR c (3 DOWNTO 0);
    c (4 DOWNTO 1) <= (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
    cout <= c(4);
end Behavioral;

Hello, it's the first time im using this forum. I'm doing a wallace tree multiplication on VHDL. The code above is the code for a full adder. I would like to know how do we call a function/component in a main code ? (like in C programing). I would to call this full adder in my main code. (Sorry for my english if there is any mistake, im french)

Bill Lynch
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user2140483
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2 Answers2

5

You call functions in VHDL just as you do in C - either to initialise constants, signals or variables, or as sequential statements within a process. But that's not important just now.

But you don't call components! That would be like calling an object in C++ - it makes absolutely no sense!

In VHDL you can instantiate components or (simpler!) just entities, and use signals to interconnect their ports. This is (very very crudely) more like declaring objects and sending messages in an object oriented language. This is called "structural VHDL" and often appears at the top level of a VHDL design, to create and interconnect components like CPU, memory interface, FFT processor etc.

Given your entity 

entity Lab3_Adder1 is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end Lab3_Adder1;

I could build an 8-bit adder for example as follows:

entity Adder_8bit is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
           s : out  STD_LOGIC_VECTOR (7 downto 0);
           cout : out  STD_LOGIC);
end Adder_8bit;

architecture Structural of Adder_8bit is

signal carry_int : std_logic;   -- between lower and upper halves

begin
-- We need to create and connect up two adders

LSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => cin,
           a  => a(3 downto 0),
           b  => b(3 downto 0),
           s  => s(3 downto 0),
           cout => carry_int
    );
MSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => carry_int,
           a  => a(7 downto 4),
           b  => b(7 downto 4),
           s  => s(7 downto 4),
           cout => cout
    );

end Structural;
0

You can define VHDL-Functions which replace combinational circuits and which can be called anywhere in the main VHDL-Code similar to C functions.

You need to define a package first where the function definitions go.

======= myAdders.vhdl ==============

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

package myAdders is

function Lab3_Adder1( cin : in  STD_LOGIC;
a : in  STD_LOGIC_VECTOR (3 downto 0);
b : in  STD_LOGIC_VECTOR (3 downto 0);
s : out  STD_LOGIC_VECTOR (3 downto 0)) return std_logic;
end Lab3_Adder1;

end myAdders;

package body myAdders is


function Lab3_Adder1 ( cin : in  STD_LOGIC;
a : in  STD_LOGIC_VECTOR (3 downto 0);
b : in  STD_LOGIC_VECTOR (3 downto 0);
s : out  STD_LOGIC_VECTOR (3 downto 0)) return std_logic is
variable c: std_logic_vector(4 downto 0);
begin

c(0) := cin;
s := a XOR b XOR c (3 DOWNTO 0);
c (4 DOWNTO 1) := (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
return c(4);
end Lab3_Adder1;


end myAdders;

======= topLevel.vhdl ==============

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.myAddres.all;


entity TopLevel is
    Port ( 
           cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           c : out  STD_LOGIC_VECTOR (3 downto 0)
           );
end TopLevel;

architecture Structural of TopLevel is

signal carry : std_logic;  

begin

carry <= Lab3_Adder1(cin, a, b, c);

... and so on ...

end Structural;
EHunter
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