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I am looking out for a way so that I can send an input value from nios as a parameter to a verilog module.

or

Any other ways of assigning verilog parameter from input.

Morgan
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vlsi2013
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2 Answers2

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It certainly can't pass a parameter since those options change the behavior of the Verilog at synthesis time (i.e. before you even load it in the chip). Do you mean to ask how to use NIOS II to set input values?

Ben Jackson
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    Hi Ben , Thanks for the reply .I am looking out something as below :- The project uses a constant value for generating some clock . This value has to be chosen by the user ( may be i can give some predefined constant values, but user has to selects one of these and this is what i am looking forward). Ex . I have different constant values ( 1500 ,3600 , 3567 , etc ) and i need to choose only one constant value at a time based on a select logic .Like if input is 0 , then parameter is 1500 .... I was looking out to figure out the solution and thought nios could offer some solution. – vlsi2013 Mar 01 '13 at 06:17
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    If you have something like `parameter CLOCK = 1500`, you cannot change that at runtime. If you have `input [12:0] clock` you could hook that up to NIOS II. – Ben Jackson Mar 01 '13 at 06:25
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    I have `parameter CLOCK1 = 1500` `parameter CLOCK2 = 3600` `parameter CLOCK3 = 3564` etc I also have an [3:0] input . i need to choose Clock parameter value based on input . for Ex . if input == 0000 ; `DIV= CLOCK1 ` if input == 0001 ; `DIV = CLOCK1 ` DIV is also a parameter which will be passed to another module – vlsi2013 Mar 01 '13 at 06:45
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    Parameters are synthesis time constants (synthesis is like compiling for Verilog). You can't modify them with runtime values like inputs. You would have to rewrite the module taking `DIV` to take `input [...] DIV` rather than `parameter DIV` – Ben Jackson Mar 01 '13 at 06:49
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As Ben Jackson has already mentioned parameters are constants and can not be changed at runtime. What you need is a low bit width input which selects the predefined value from a look up table (LUT).

module lut(
  input   [1:0] sel,
  output [31:0] val
);

localparam CLOCK1 = 1500 ;
localparam CLOCK2 = 3600 ;
localparam CLOCK3 = 3564 ;
localparam CLOCK4 = 4048 ;

always @* begin
  case (sel) 
    2'b00 : val = CLOCK1;
    2'b01 : val = CLOCK2;
    2'b10 : val = CLOCK3;
    2'b11 : val = CLOCK4;
  endcase
end
Morgan
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