I am looking out for a way so that I can send an input value from nios as a parameter to a verilog module.
or
Any other ways of assigning verilog parameter from input.
It certainly can't pass a parameter since those options change the behavior of the Verilog at synthesis time (i.e. before you even load it in the chip). Do you mean to ask how to use NIOS II to set input values?
As Ben Jackson has already mentioned parameters are constants and can not be changed at runtime. What you need is a low bit width input which selects the predefined value from a look up table (LUT).
module lut(
input [1:0] sel,
output [31:0] val
);
localparam CLOCK1 = 1500 ;
localparam CLOCK2 = 3600 ;
localparam CLOCK3 = 3564 ;
localparam CLOCK4 = 4048 ;
always @* begin
case (sel)
2'b00 : val = CLOCK1;
2'b01 : val = CLOCK2;
2'b10 : val = CLOCK3;
2'b11 : val = CLOCK4;
endcase
end