Digital logic is the representation of signals and sequencing of a digital circuit. It is the basis for digital computing. (Note: There is the Electrical Engineering Stack Exchange website which is more suited to asking questions on hardware.)
Questions tagged [digital-logic]
229 questions
1
vote
1 answer
Problem while implementing JK-Flip Flop in VHDL
I'm trying to implement JK flip-flop in VHDL, and here is my code:
library ieee;
use ieee.std_logic_1164.all;
entity jk_flip_flop is
port(
J, K : in std_logic;
clk : in std_logic;
Q, Q_bar : out std_logic
);
end…
theCursedPirate
- 165
- 1
- 1
- 7
1
vote
1 answer
Capturing the right posedge clock in Quartus waveform
I am using Quartus Prime Lite 19.1.0.
module memory_address_register1 #(
parameter ADDR_WIDTH = 4
)(
input clk, rst, load,
input [ADDR_WIDTH-1:0] add_in,
output reg …
Blaco
- 109
- 8
1
vote
0 answers
VHDL State Machine Skipping Intermediate State
I am trying to implement the controller for a simple CPU in VHDL. The controller is modeled as an ASM that waits in a decode state until it receives the start signal. The next state that it progresses into depends on the machine code received and…
ajflj
- 115
- 1
- 2
- 7
1
vote
1 answer
ALU using modules in Verilog
I am implementing a 4-bit ALU using Verilog.
I am getting some weird results in testbecnh.
Here is code for the ALU:
`include "ripple_carry_adder_4.v"
module alu_4(A, B, CTRL, Y);
input [3:0] A, B;
input [3:0] CTRL;
output reg…
yukinoda
- 11
- 2
1
vote
1 answer
2's complement std_logic_vector to unsigned number
I have a 4 bits std_logic_vector whose values are represented in 2's complement. And I want to extract it's unsigned value
signal FOURbits_2scomplement : std_logic_vector(3 downto 0);
signal THREEbits_number : unsigned(2 downto…
JeanDujardin
- 162
- 1
- 10
1
vote
0 answers
Register values not showing at the correct time in testbench simulation
Based on research, the input value to a flip flop is read during one rising/falling edge and output at the next rising/falling edge, however, I'm not seeing this behavior in my test bench.What I believe I'm seeing is that the output values are being…
Tellrell White
- 65
- 1
- 8
1
vote
1 answer
Converstion from SOP to POS using boolean algebra
The question is this:
wx'y'+wyz'+w'x'z
I tried this technique but got stuck:
w(x'y'+yz')+w'x'z
(w+x'z)(w'+x'y'+yz')
(w+x')(w+z)(w'+x'y'+yz')
but this is not correct since it should end with 4 pos terms.
How can I convert this from sum of products…
Srinivas NanneBoina
- 11
- 1
1
vote
2 answers
Chisel3 REPL Vec assignment into module only works after eval
If we run the following Chisel3 code
class Controller extends Module {
val io = IO(new Bundle {
})
val sff = Module(new SFF)
val frame: Vec[UInt] = Reg(Vec(ProcedureSpaceSize, Integer32Bit))
for(i <- 0 until ProcedureSpaceSize)
…
apen
- 672
- 4
- 14
1
vote
0 answers
Smart way of simplifying logical circuits by hand?
Let's say I have the following logical circuit:
How can I create a simplified version (assuming that one exists) without laboriously creating a truth table for it? I was thinking of perhaps writing the boolean expression as a sum of minterms to…
daedsidog
- 1,732
- 2
- 17
- 36
1
vote
1 answer
8 bit carry lookahead adder error with SystemVerilog in Questasim using two 4 CLA's
I keep getting an error when I simulate the CLA4Top, CLA8Top and the test.
The testbench was given and the entire project compiles. For the CLA4Top I thought it looked like "cout" is coming out to be correct but "sum" is not matching the expected…
MignolaFan
- 31
- 4
1
vote
1 answer
Digital Logic - realizing full adder using NAND gates?
I am stuck while solving this question,
What is the minimum number of 2 input
nand gates required to realize
I found the answer when there is no limit on the number of inputs, but cant find the answer when the constraint "2 input nand gate" is…
hue
- 1,759
- 3
- 27
- 37
1
vote
1 answer
Digital Logic Puzzle, "2 out of 10 voting" logic
I am tring to implement kind of "2 out of 10 voting" logic. This logic simply says if atleast 2 inputs out of given 10 inputs are "ON" then only output must be "ON".
So I have 10 digital inputs which needs to be mixed with logic gates OR, AND, NAND…
Nains
- 258
- 2
- 15
1
vote
3 answers
How can I set normal clock input?
input
clk ( clock ) :
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ...
required output :
F :
0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 ...
How can I get that output over using combinational and sequential circuit (logic…
user478571
1
vote
1 answer
ERROR: 'Checker 'xor_module_b' not found. Instantiation 'x0_1' must be of a visible checker.'?
What is this error 'Checker 'xor_module_b' not found. Instantiation 'x0_1' must be of a visible checker.'? I am writing verilog code in behavioral model by using module instantiation. While compiling i am getting the error. Portion of code and…
Ankit Mahajan
- 13
- 1
- 4
1
vote
1 answer
No state initialization or change for FSM in verilog
`timescale 1ns/1ps
module div_by_3(
input clk,
input rst,
output y
);
reg [1:0] state, nextstate;
//state encoding
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
//state registers
always@(posedge clk or negedge…
Amuly Pandey
- 19
- 4