2

i need a frequency divider in verilog, and i made the code below. It works, but i want to know if is the best solution, thanks!

module frquency_divider_by2 ( clk ,clk3 );
output clk3 ;
reg clk2, clk3 ;
input clk ;
wire clk ;
initial clk2 = 0;
initial clk3 = 0;
 always @ (posedge (clk)) begin
   clk2 <= ~clk2;
 end
 always @ (posedge (clk2)) begin
  clk3 <= ~clk3;
 end
endmodule

the circuit generated by quartus:

enter image description here

Guilherme Stéfano
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  • **One** `J-K flip flop` is [enough](http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/bincount.html#c3) to create frequency divider (by 2). Your code is synthesized **two** `D flip flops`, so it's not the best solution. – Qiu Jun 03 '14 at 19:32
  • Are you asking if this is the best way to divide a clock, in logic, with verilog? Or if this is the best way to get a clock running at 1/2 the speed of the original? There many cases when you wouldn't want to use a clock generated by logic like this. – Will Jun 05 '14 at 10:09
  • In verilog, what is best way to get a clock running at 1/2? – Guilherme Stéfano Jun 06 '14 at 12:58
  • Do you mind telling me how to generate circuit from verilog code in quartus? – 齐天大圣 Feb 09 '15 at 04:13

1 Answers1

5

Your block divides the frequency by 4 not 2. There is actually quite a good description of this on Wikipedia Digital Dividers. Your code can be tidied up a bit but only 1 D-Type is required, which is smaller than a JK Flip-flop so is optimal.

module frquency_divider_by2(
  input      rst_n,
  input      clk_rx,
  output reg clk_tx
);

always @ (posedge clk_rx) begin
  if (~rst_n) begin
    clk_tx <= 1'b0;
  end
  else begin
    clk_tx <= ~clk_tx;
  end
end

endmodule

When chaining these types of clock dividers together be aware that there is a clk to q latency which is compounded every time you go through one of these dividers. IF this is not managed correctly by synthesis the clocks can not be considered synchronous.

Example on EDAplayground, should open the waveform when run.

Morgan
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