How would you handle a special case in this digital logic system?

Question

I posted this digital logic diagram as an answer to another stackoverflow question. It describes a logic system which will be coded in Verilog or VHDL and eventually implemented in an FPGA.

alt text http://img145.imageshack.us/img145/5125/bitshifterlogicdiagramkn7.jpg

The numbered boxes in the diagram represent bits in a field. Each field has K bits, and the bits for current and mask will be provided by a computer system (using a latched register or equivalent). The bits in next will be read back into that same computer system.

The solution that I posted works as long as there is at least one bit set in the mask field, and there is exactly one bit set in the current bit field. The idea is that the next bit field will become the current bit field after the computer system has performed some task (a scheduling operation, in the original question).

So, my question is this: How would you modify this system so that it properly handles the special case where the current bit field is all zero (no bits set)? As it stands, if all bits in current are zero, the output will also be zero, no matter what the bits in mask are set to.

Ideally, if current is all zeroes, the lowest set bit in mask should be set in next. The system should also still remain scalable to any number of bits (K) without having to add exponentially more logic gates. The spirit of the original question was to come up with a solution that would be straightforward to implement for any number of bits.

See also: this stackoverflow question

paxdiablo · Accepted Answer · 2009-01-28T11:16:20.490

2

For me, I would tell the user of the FPGA that they must have one of the bits set to 1 on entry.

However, if that's not your preferred solution, what's wrong with the idea of pre-feeding all the Current inputs initially into a big NOR gate (so that the output is true only when all inputs are false). All Current lines also continue through to their AND gates with the exception that Current[1] is OR'ed with the output of our NOR gate before entering it's AND gate

That way, Current[1] would be true entering the AND gate, if all Currents are false.

Keep in mind that I understand boolean algebra but I've never worked on raw hardware - I'm guessing you'll need to buffer all the input signals into the AND gates to ensure correct timing but i suspect you'll know that better than I.

The following diagram is left in in case SO fixes its code/pre blocks - the latest SO update seems to have stuffed them up (leaving them proportional, not fixed-width, font). Anyway, eJames' graphical diagram is better.

Here's my diagram, slightly less elegant than yours :-):

               +-------------------+
               |                   |
               |     +----         |
Current[1]-----+------\   \        |
                       |NOR|o--+   |
Current[2-k]---+------/   /    |   |
               |     +----     |   |
               |              +\   /+
               |              | \_/ |
             +---+            |  OR |
              \ /Buffer        \   /
               +                ---
               |                 |
             +---+             +---+
             |2-k|             | 1 |    <- These signals feed 
             +---+             +---+       into your AND gates.

edited Jan 28 '09 at 11:16

answered Jan 28 '09 at 06:10

paxdiablo

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Good solution! The K-input NOR gate can be refactored into an extra OR gate at each bit, which keeps the system modular by number of bits. – e.James Jan 28 '09 at 06:29
Also, setting current[1] neatly selects the lowest set bit in the mask as the bit to set in next. I like it :) – e.James Jan 28 '09 at 06:30
Is it a requirement for the K+1-bit circuit to be a simple extension of the K-bit circuit? If you're asking for an HDL implementation, you should probably let your synthesis tool do its thing on a behavioral description and constraints; it can usually do a better job than we can. – Matt J Jan 28 '09 at 06:33
eJames, I don't understand your refactor comment (educate me :-). You need to treat Current as a *unit* so I can't see how passing *individual* lines will work ?? – paxdiablo Jan 28 '09 at 06:35
A synthesis tool may also figure out a way to trade off more hardware to shorten the O(K) critical path in the circuit diagram above, if that's advantageous. This is a common technique for priority encoders/schedulers, as they are often the critical path in the larger circuits they schedule. – Matt J Jan 28 '09 at 06:36
Or do you mean: replace the buffers with OR gates where the other input is the negated output from NOR? – paxdiablo Jan 28 '09 at 06:39
@Pax: It looks like you have an answer already, but I was working on an image, so I'll post it anyway, for the sake of other readers: http://stackoverflow.com/questions/486473/how-would-you-handle-a-special-case-in-this-digital-logic-system#486723 – e.James Jan 28 '09 at 07:05
@Matt J: You're right about a synthesis tool being the way to go. I wanted the diagram to describe the inherent algorithm in a way that humans could understand so that the programmer would know how to write the logic description for the synthesizer :) – e.James Jan 28 '09 at 07:08

How would you handle a special case in this digital logic system?

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