A global provider of Electronic Design Automation (EDA) software and engineering services. It produces software for designing integrated circuits (also known as "chips"), and printed circuit boards.
Questions tagged [cadence]
109 questions
0
votes
1 answer
How to continue running the script inside the new shell that has been called from the same script?
I am a super newbie in this area so I apologize in advance for any dumb thing I might say! :D
I work with Cadence's RTL Compiler and I am trying to automate the process of synthesizing so many designs with different sizes located in different…
0
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1 answer
Illegal operand for constant expression
I'm trying to build a task, which must delve into some hierarchy, that can concisely compare different pins on a particular instance. In particular, I'd like to do something like the following:
task check_expected;
input integer pin;
input [9:0]…
user3570982
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1 answer
Find unused variables
I'm using the following tools for programing in verilog+system-verilog and I'm wondering which can detect which variables are not being in use:
Eclipse
Eclipse DVT extension
Cadence tools
user2692669
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2 answers
Synthesis error on a CASE statement in Verilog
I m new in Verilog and I would like to know your opinion about an error I get when trying to synthesize the part of my code cited below:
input [31:0] A;
reg [31:0] X,Y;
reg [15:0] width;
input action;
always@*
begin
width= A [31:16];
…
marsia
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2 answers
Command to send signals to waveform in SimVision
Is there a (Tcl-)command I can use to send signals to waveform in SimVision?
Of course You can rightclick them and then select "Send to WaveForm Window", but to do that each time you start a simulation will be a pain.
In Modelsim you can easily use…
Sadık
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3 answers
Is there a way to use one testbench for different simulators if both simulators need their own packages to be used?
My testbench uses a function that is defined in a modelsim package (init_signal_spy). So I can't use this testbench with a different simulator than ModelSims vsim, for example Candence's ncsim. But there is an equivalent function for ncsim…
Sadık
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- 89
0
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1 answer
SystemVerilog: Parameter used in concatenation gives error with irun
Cadence irun gives error for below code, where fifo_depth_base2 is parameter as below:
ncvlog: *E,NONOWD (buff_mgr.v,17|46): Illegal use of a constant without an explicit width specification [4.1.14(IEEE)].
I can understand this error, but my…
user3242374
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- 3
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2 answers
Line overflow in Cadence EDI
I am working on a script in Cadence EDI tool (this is TCL based i.e. the EDI shell is TCL based). My code looks something like-
namespace eval clockgatecloning {
....
.....
......
...
}
There are a number of nested statements, procs calling each…
Ashish Shukla
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- 3
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2 answers
Infinite Loop in TCL/EDI
I am writing a script in TCL that is sourced into Cadence's Encounter Digital Implementation Shell. It recursively executes a number of TCL procs and all of a sudden exits the code saying- 'Too many nested evaluations (infinite loop?)'. I located…
Ashish Shukla
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- 3
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1 answer
VHDL code in NCLaunch giving errors not given in Xilinx
I am trying to make a dataflow design for a comparator in VHDL. It compiles and simulates fine in Xilinx, but I have to use Cadence/NCLaunch. When I copied the same code to gedit and ran it, it gives an error about a semicolon.
my code is :
library…
DDauS
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- 11
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1 answer
Adjusting the operating frequency of a module in Verilog
I am creating a fairly complicated module which involves timing analysis of 2 Modules each having their own algorithm, but take in 2 signed numbers as inputs and output a signed number.
I am designing this module for an FPGA in Verilog using Xilinx…
Prashant Vaidyanathan
- 468
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0
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1 answer
C# to call Cadence Allegro with SKILL code function
I am trying to make some calls to Cadence Allegro from C#, I have some C++ examples but they are very incomplete. I don't see anything on S/O with this, some Allegro... But if anyone has ever called up a Allegro PCB etc.. , can you point me in the…
Tom Stickel
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0 answers
Can SimVision automatically find hold time violations and highlight or tell me where it happend?
I have a scan chain that contains thousands of flip-flops or registers, and I need to find the hold time violations. The file I have is a .trn file which contains the waveforms. I also have a .svcf file which automatically displays the ports,…
myles_uy
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-1
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1 answer
Do System Verilog coverpoints and covergroups work for real variable types?
I'm looking into using coverpoints and covergroups for mixed signal verification in Cadence to verify some constrained random classes I've written. However, I haven't been able to find online if coverpoints can be used for reals. In fact, I've…
Kat
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- 1
-1
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1 answer
Cadence Virtuoso Layout XL
I am new to Cadence Virtuoso Layout.Is there any book or complete educational videos for Cadence Virtuoso Layout design? I have some DRC errors on my design and need to know how to solve the errors in different metal layers.
Ashkan
- 1