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Questions tagged [cadence]
109 questions
0
votes
1 answer
gm/Id design characteristics
What are the limitations of the gm/id based analog design methodology employed for sub-micron process nodes? I was reading a research paper that mentioned the design methodology is restricted only to class A devices.
Yashas Lr
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1 answer
How to Identify values from characteristic data for Walk Run Stride bluetooth sensor
I am developing a workout app with sensor connectivity and able to read and get data for Heart rate sensor but for stride sensors (walk/Run) facing problem to map the values given by sensor characteristic.
How will I get Speed, cadence, steps per…
Jagdev Sendhav
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2 answers
Cadence IUS simulator options
What is the difference between -INcdir and +incdir+ options in NC simulator?
Below is the example command from the Makefile. As far as I know the testbench directories are included using -INcdir and the source code file directories are included…
Sreejin TJ
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- 12
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2 answers
Combining coverpoints to create an aggregate
`define A 'd1
`define B 'd2
`define C 'd3
`define D 'd4
`define E 'd5
`define F 'd6
`define I 'd7
`define J 'd8
module testModule(input clk,
input CReset,
input[4;0] Opcode_P0I1,
…
Sparsh Gupta
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1 answer
How to compare each bits of a 32 bits number with another 32 bits number?
I am thinking compare each bits of a 32 bits number with another 32 bits number.
eg. check that ins.dout_1 == (ins.din1_1 + ins.din2_1)
Which dout_1, din1_1 and din2_1 are all unsigned integer of 32 bits.
I want to check for each bits from 12…
Harvey Wang
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- 1
0
votes
1 answer
How to run e file one by one? Not in parallel test
I am new to specman, I am now writing a testbench which i want to give many specific test cases to debug a calculator.
For example,
I have two files, the first one called "test1" and the second called "test2".
Here is my code for "test1":
extend…
Harvey Wang
- 5
- 1
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1 answer
Error in ncelab: F*MISLUN: missing top level module, design unit name
I am trying to implement a reconfigurable module which changes its configuration according to user setup. Where I will have a huge if else ladder. When an user decides to shift the bits by 4 bits to right, all the values inside of the if else…
Shaown
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- 12
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1 answer
how to run multiple sp file using spectre
I have a bunch of .sp files that need to be simulated with Cadence Spectre. Instead of run spectre as --
run spectre 1.sp->exit->run spectre 2.sp->exit->...
-- is there some kind of batch mode in Spectre so that i can launch Spectre once and…
LGMchili
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- 6
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1 answer
Why am I getting "debug domain is off" error message when using Xtensa Tensilica OCD?
I'm trying to start Tensilica's Xtensa OCD Daemon by typing xt-ocd.exe in the appropriate directory but I keep getting a warning stating that "Debug domain is OFF (PWRSTAT:0x0)!" followed by an error message saying "Cannot set JTAG Usable bit while…
Arash Fotouhi
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Is it possible to fully compile a module and then instantiate it in a testbench separately?
Is it possible to make a fully compiled and standalone version of an RTL module, like a snapshot in Cadence terms, and then later instantiate this compiled module into a testbench?
Ultimately, running another compile step to create a final snapshot…
Ginty
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1 answer
How to use an ideal diode in the virtuoso candence
I use the ideal diode in the virtuoso candence,but the log file show me an error when i simulate the circuit.
**error** (input.ckt:44) definition of model mydiode not found.Please specify a defined model name.
Here is my diode information,i don't…
XM551
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- 5
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1 answer
name of skill function get list of master children layout cells used in current design
Does Cadence Virtuoso have a skill function to get list of master children layout cells used in current design?
I've tried to work with
ddGetObjChildren
but this function returns children of datatypes for my top cell: schematic, abstract , etc.
I…
Roman Kaganovich
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Setting Probes for SimVision in SystemVerilog Code
I'm trying to probe the systemverilog signals by using irun .
I came across the some example to dump wave as the below ,when I googling.
initial begin
$recordfile("sv_wave"); …
start01
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1 answer
How to make $display messages show up in SimVision console
I have to use the Cadence program suite to complete a Verilog class assignment and I'd like to know why $display statements in the very simple mock-testbench I have created do not produce output in the SimVision console window.
My workflow goes like…
Peter
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1 answer
How to generate a duplicate random number sequence between SystemVerilog simulators?
I cowork a SystemVerilog project with someone. However, I am used to use Synopsys VCS SystemVerilog simulator and he is used to use Cadence INCISIVE irun.
One testbench module uses random numbers for generating test input pattern to top design…
Meng-Yuan Huang
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