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Cadence irun gives error for below code, where fifo_depth_base2 is parameter as below:

ncvlog: *E,NONOWD (buff_mgr.v,17|46): Illegal use of a constant without an explicit width specification [4.1.14(IEEE)].

I can understand this error, but my question is how would I otherwise assign it for parameterized design.

// rd pointer and read logic
always @(posedge clk or posedge rst) begin
    if(rst) rd_ptr <= 0;
else begin  
    case({flush, rd})
        2'b10, 2'b11: rd_ptr <= {fifo_depth_base2{'b0}}; // error here
        ...
 endcase
end
end
Greg
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user3242374
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  • I think in SystemVerilog, when using a construct like this `fifo_depth_base2{'b0}`, fifo_depth_base2 should be a constant. You can probably use a for loop to make it parameterized, or just `rd_ptr <= '0`. – Ari Apr 28 '14 at 18:38
  • See this: http://stackoverflow.com/questions/23239366/how-to-generate-a-set-of-continuous-one-in-verilog – Ari Apr 28 '14 at 18:40
  • @Ari, `fifo_depth_base2` is a parameter, so it is already a constant. – Greg Apr 28 '14 at 18:43

1 Answers1

3

You are missing a 1 before 'b0. The simulator doesn't know the bit size of 'b0 because it is not specified.

{fifo_depth_base2{'b0}}; should be {fifo_depth_base2{ 1'b0}};

With SystemVerilog you can use: rd_ptr <= '0;, where '0 means fill zeros

Greg
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