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Questions tagged [amba]

The ARM Advanced Microcontroller Bus Architecture (AMBA) encompasses (among others) the APB, AHB and AXI interconnect types, commonly seen on ARM processors.

Specifications can be found here.

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JTAG instructions to access the ARM-Cortex-M4 registers

I have a debug probe that allows me to perform JTAG operations (Instruction and Data scans). Having this, I would like to know how do I get to the MCU registers knowing that the SOC I am using implements the JTAG Debug Port defined by the ARM…
Ricardo Alejos
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ARM vs x86 IO mappings

I was looking at Raspberry Pi data sheet. On the page BCM ARM PERIPHERALS, A diagram showing mappings from Physical address to ARM virtual address, the mappings are constant. That is: ARM Physical address 0x20000000 (IO base address) gets mapped…
RootPhoenix
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Coherently understand the software-hardware interaction with regard to DMA and buses

I've gathered some level of knowledge on several components (including software and hardware) which are involved in general DMA transactions in ARM based boards, but I don't understand how is it all perfectly integrated, I didn't find a full…
Bush
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Ready and valid

Does has any difference in Request and Valid signal for handshake protocol ? I am looking for the protocol which has request and valid both signals. Are any protocol used in VLSI filed ? does request and valid are same or different.
Charmi Toliya
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How to check if write channel in AXI is working fine in my testbench?

I want to write on AXI memory by an AXI master vip and check if the write has been done correctly without reading it back by AXI master. I just want to check if a transaction has been written correctly, how to do that ? I know I can check data…
Grace90
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What does "observed" mean here in the AXI standard?

I'm reading section A6.4 "Slave ordering" of AXI standard, but I don't quite understand what the word "observed" mean in the standard text: A6.4 Slave ordering To meet the requirements of the ordering model, a slave must ensure that: • Any write…
zzzhhh
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Byte Masking AxiStream: How to mask tdata with tkeep systemverilog

In AxiStream the tkeep value in each transfer denotes the valid bytes in the tdata field of the same transfer. In systemverilog i want to use tkeep to mask (set to 0) the invalid bits in the tdata field. If tkeep denoted invalid bits then I could…
Guilty
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AHB Bus : Implementing a narrow slave on a wide bus

I see this image in ARM's AHB spec. This is basically an example of how we can use the AHB fabric to connect with narrower slave. Here I am not able to understand the usage of haddr[2] as a mux select. How will this bit help us in figuring out if we…
Shashank Shekhar
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Why data cannot be written on base address+1 on ASB

I'm working on my project about AHB protocol. What I'm doing is make IP blocks with AHB system and write/read data using SDK(Vitis). The base address is assigned to 0x43C0_0000. If I write data on base address with Xil_Out it works. However, when I…
K C
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MESI protocol snoop implementation issue

I have a MESI protocol question. Assume that I have two cores (core 1 and 2) and each core has its own l2 cache. When two core has the same data and cache lines are in status S, meaning they both have clean and the same data. At t=0, core 1 writes…
rosepark222
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How to make ACLK centric data transfer

In the AXIS stream speck the ACLK is defined as: The global clock signal. All signals are sampled on the rising edge of ACLK. Which means that it is assumed that AXIS master and slave are receiving the same ACLK. Can you please help understand…
haykp
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example extending LEON SOC with custom peripheral, AMBA AHB slave

Has anyone here extended LEON3 softcore with custom hw? I'm looking for basic example how to add custom peripheral to AMBA AHB bus
laki
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Why master is incrementing Address in AMBA AHB Burst transfer?

In AHB burst mode, master has to give only starting address and slave has to calculate the remaining address. But in the picture below (from AHB specification) address is incrementing at HAddress pin for every clock. Why? Am I wrong?
tollin jose
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AXI4- explanation regarding transaction, data transfer, burst and beats

I'm little confused regarding the relationship between the above concept. Does burst is just a type of AXI transaction> Can it take more the one clock transaction? What is exactly a beat? does it contain address and data?
sara8d
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AXI bus to Wishbone Wrapper

Could anyone please tell me about the AXI bus and its signals. I would also want to know about AXI bus to wishbone bus wrapper to implement it in VHDL. I am looking at the implementation of a register in FPGA and then give the corresponding…
Tech Geek
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