I'm working on my project about AHB protocol.
What I'm doing is make IP blocks with AHB system and write/read data using SDK(Vitis).
The base address is assigned to 0x43C0_0000.
If I write data on base address with Xil_Out it works.
However, when I give 0x43C0_0000 +1 to Xil_Out, it does not work.
By trial and error, I found that only address on 0x43C0_0000 + 4*n works.
Why writing data not on that range does not work?
Most computer addressing schemes state that +1 address offset means access to one byte of information. If in your design AHB bus is 32-bits write access with an address offset 1 should put your data into D[15:8] bits assuming little-endian mode of the AHB bus. In the AMBA world, that Xilinx has adopted, such access called narrow access meaning that 8 bits are less than the full 32-bits. Hence, writing of one byte should leave the remaining 24-bits in this memory location intact. This is typically accomplished by having byte selects which AHB bus does not have while its cousin AXI does have: https://developer.arm.com/documentation/ddi0243/c/AHB-Components/Bus-matrix/Signal-descriptions
It is very likely that Xilinx design does not support narrow AHB accesses, while you can still write entire 32-bits at the address offset(s) 4*n as you have found out experimentally. However, I would rather not do experiments and just agree on one type of computer bus, but we humans rarely agree. Just look at what we do or do not do with facemasks during COVID-19 pandemic.
