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How to generate pseudo random number in FPGA?

starblue
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    For those doing searches for random numbers in FPGA, they will be able to far more easily find this question. Thus, I won't vote to close as a duplicate. – AlbertoPL Jul 14 '09 at 14:19
  • Perhaps those who are looking for FPGA in stackoverflow would like to know about a specific site : [Logic Design proposal](http://area51.stackexchange.com/proposals/20632/logic-design?referrer=YVw0qLaS2iiFAaI1gMp5oQ2) – woliveirajr Oct 04 '12 at 14:42
  • oh, good that it was asked here and not in this Area 51 site. It was DELETED ;) – VP. Feb 17 '17 at 22:35

4 Answers4

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This has been covered (I'd go for an LFSR): Random number generation on Spartan-3E

Community
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Marty
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5

There's an excellent Xilinx application note on generating pseudo-random number sequences efficiently in an FPGA. It's XAPP052.

geschema
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4

If it's not for cryptography or other applications with an intelligent adversary (e.g. gambling) I'd use a linear feedback shift register approach.

It only uses exclusive or and shift, so it is very simple to implement in hardware.

starblue
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1

As others have said, LFSRs can be used for pseudo random numbers in an FPGA. Here is a VHDL implementation of a maximal length 32-bit LFSR.

process(clk)

  -- maximal length 32-bit xnor LFSR based on xilinx app note XAPP210
  function lfsr32(x : std_logic_vector(31 downto 0)) return std_logic_vector is
  begin
    return x(30 downto 0) & (x(0) xnor x(1) xnor x(21) xnor x(31));
  end function;

begin
  if rising_edge(clk) then
    if rst='1' then
      pseudo_rand <= (others => '0');
    else
      pseudo_rand <= lfsr32(psuedo_rand);
    end if;
  end if;
end process;
mksuth
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