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I am looking for a way to generate random numbers in FPGA for use as an IV for cryptographic applications. However, the answers to similar questions i found on Stackoverflow so far generate random numbers from a "Fixed SEED" which is not at all suitable for a cryptographic application. Pointers to two of such answers are as follows:-

Random number generation on Spartan-3E and How to generate pseudo random number in FPGA?

Hope to get some helpful answers in this regard from the community! Thanks

Community
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Kaka
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  • Try this: *[Compact FPGA-based True and Pseudo Random Number Generators](http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.444.6979&rep=rep1&type=pdf)* – r3mainer Jan 06 '17 at 09:23
  • I'm voting to close this question as off-topic because StackOverflow is a development Q/A site - this doesn't include FPGA design. Why not try [EE](http://electronics.stackexchange.com/questions/tagged/fpga)? – Maarten Bodewes Jan 06 '17 at 15:40
  • So, an [unfixed seed](https://i.stack.imgur.com/WZeRF.jpg) and an appeal to an authoritarian source ([Approved Random Number Generators for FIPS PUB 140 - 2, Security Requirements for Cryptographic Modules](http://csrc.nist.gov/publications/fips/fips140-2/fips1402annexc.pdf))? (Leads to [NIST Special Publication 800 -90A Revision 1 Recommendation for Random Number Generation Using Deterministic Random Bit Generators](http://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-90Ar1.pdf)). –  Jan 06 '17 at 15:56

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The issue is that you need some random entropy in order to generate a cryptographically secure pseudo number generator (CSPRNG). That generally is obtained by using portions of real-time events from am OS which may include interrupt timing and other hard things that are hard for am attacker to influence.

A FPGA in isolation is not going to have this source of entropy.

There are also several ways to create True Random Numbers Generators such as using multiple free running oscillators.

zaph
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