How to get xilinx FPGA (spartan6 series) SRAM random value at power?

Question

Xilinx FPGA at power ram IP will be initialized to 0, instead of electronic random number，but I need the electronic random number.

Answer 1

The contents of block RAMs in a Xilinx FPGA is part of the configuration bitstream. By default (meaning, if you did not specify anything in your design), that content is all zeroes. This is by design, and allows for example the block RAMs to be used as ROMs, or as memory for a soft processor (e.g. MicroBlaze) that is pre-initialized with bootloader code.

How to accomplish what you want depends on how random you actually need the content to be.

Pre-Generated Random Data

If it is acceptable for your application to have the same contents at each boot up, you can pre-generate random data and initialize your RAM content with that data when you create it. This is the simplest option. If you have a look at the description of the RAMB8BWER and RAMB16BWER primitives in the Spartan-6 Libraries Guide for HDL Designs, you will see the INIT_00 to INIT_3F and INITP_01 to INITP_07 generics serve exactly this purpose.

9-kb RAM (RAMB8BWER) on Spartan-6

There is a design advisory from Xilinx (AR# 39999 9K Block RAM Initialization Support) that states that a 9-kb block RAM will not be initialized reliably as described above. The exact behaviour is not described, only that the device "can fail to initialize user-specified data or default values", so I would not infer from that that the block RAM is reliably uninitialized either. One of the suggested workaround is to use the 18-kb block RAM instead (RAMB16BWER primitive).

Dynamic Data

If it is not acceptable for your application to have the same contents at each boot up, you will need to actually code some sort of state machine to initialize the RAM contents before use. How complex this has to be will depend on your requirements for randomness. You can have a look at the following question for pointers: How to generate pseudo random number in FPGA?.