ARM Cortex-A76

ARM Cortex-A76
General information
Launched	2018
Designed by	ARM Holdings
Performance
Max. CPU clock rate	to 3.0 GHz in phones and 3.3 GHz in tablets/laptops
FSB speeds	100 to 104
Address width	40-bit
Cache
L1 cache	128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core
L2 cache	128–512 KiB per core
L3 cache	512 KiB–4 MiB (optional)
Architecture and classification
Microarchitecture	ARM Cortex-A76
Instruction set	ARMv8-A: A64, A32, and T32 (at the EL0 only)
Extensions	ARMv8.1-A, ARMv8.2-A, Cryptography, RAS, ARMv8.3-A LDAPR instructions, ARMv8.4-A dot product;
Physical specifications
Cores	1–4 per cluster;
Co-processor	ARM Cortex-A55 (optional)
Products, models, variants
Product code name(s)	Enyo;
Variant(s)	Arm Neoverse N1;
History
Predecessor(s)	ARM Cortex-A75; ARM Cortex-A73; ARM Cortex-A72
Successor(s)	ARM Cortex-A77

The ARM Cortex-A76 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre. ARM states a 25% and 35% increase in integer and floating point performance, respectively, over a Cortex-A75 of the previous generation.

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