ARM Cortex-A55
The ARM Cortex-A55 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre. The Cortex-A55 is a 2-wide decode in-order superscalar pipeline.
| General information | |
|---|---|
| Launched | 2017 |
| Designed by | ARM Holdings |
| Performance | |
| Max. CPU clock rate | 1.25 GHz to 2.31 GHz |
| Cache | |
| L1 cache | 32–128 KB (16–64 KB I-cache with parity, 16–64 KB D-cache) per core |
| L2 cache | 64–256 KB |
| L3 cache | 512 KB – 4 MB |
| Architecture and classification | |
| Application | Mobile |
| Instruction set | ARMv8.2-A |
| Physical specifications | |
| Cores |
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| Products, models, variants | |
| Product code name(s) |
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| History | |
| Predecessor(s) | ARM Cortex-A53 |
| Successor(s) | ARM Cortex-A510 |
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