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Questions tagged [xilinx-edk]

The Embedded Development Kit (EDK) is an integrated development environment for designing embedded processing systems. This pre-configured kit includes Xilinx Platform Studio and the Software Development kit, as well as all the documentation and IP that you require for designing Xilinx Platform FPGAs with embedded PowerPC® hard processor cores and/or MicroBlaze™ soft processor cores.

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Type region `ilmb_cntlr_3_dlmb_cntlr_3' overflowed by 12208 bytes o

I'm trying to do an application using 4 microblazes: microblaze_0 microblaze_1 microblaze_2 microblaze_3 and I connect them using FSL connection: microblaze_0 send data to microblaze_2 through MFSL0 microblaze_1 send data to microblaze_2 through…
arrow man
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MicroBlaze is under RESET

I'm using an Atlys Spartan6 xc6slx45. I have these errors when I run the program: 1. Check whether board is connected to the system properly. 2. In case of zynq board, check whether Digilent/Xilinx cable switch settings are correct. 3. If you are…
Classe Ensi E
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Eclipse (CDT) not sending commands to GDB when debugging C++ static libraries

We are trying to debug a C++ application for a remote linux box which contains a main C++ application and some statically linked library projects. Our problem is the breakpoints which are placed inside the static library are not hit and we are…
asasamar
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Changing the MHS file in xilinx EDK 14.4 adding a port in the uart peripharal

I am trying to add a port in the uart created by xilinx-EDK (hardware design in the EDK of the hardware setup I have), I got to know by changing the MHS file I can add a port. but whenever I change the the MHS file it shows an error that i can not…
user3217310
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How to Read Data from a specific address of the FPGA QSPI Flash board?

I'm new to Vitis and XilinX-edk world. I'm working on a project and i want to implement a design that uses microblaze to do these 3 tasks : 1-Read some data from a specific QSPI Flash address. 2-Save into the BRAM. 3-Wait for 1 in a GPIO Input then…
mohamed AFASSI
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Installation Cannot be performed fix this issue before installing. Virtualization is not enabled in BIOS Please enable before installing?

I had already enabled Virualization from "BIOS". But still I am unable to install please help?? Is there is any alternate other then Xilinx.
vishal singh
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Viewing Microblaze Processor Output with out Serial Port

I am experimenting with some Old Legacy Spartan 3 , 6 and Virtex 5 Series Kits as a part of research work. I am currently designing a microblaze processor systems. Is it possible that without using RS232 cable interface I can view the results on…
Arslan Majid
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How to link source files into Eclipse based IDE

I am now at the beginning of software project for Xilinx Zynq SoC hardware platform. Xilinx company offers for software development their own Eclipse based IDE called Vitis. Due to version control reasons I need to have application source codes and…
Steve
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Stuck in API XAxiDma_BdRingFromHw, why doesn't the S2MM Block descriptor's Completed bit Set?

I am working on Zynq 7z030 and i am trying to receive data on the DDR from the PL side. I am using the AXI DMA SG poll code provided as example by xilinx on SDK. (xaxidma_example_sg_poll.c) After Configuring DMA -> Setting up the RX channel ->…
atnd
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Xilinx SDK/Eclipse Debug Configuration Issues

I'm using the Xilinx SDK (built on top of Eclipse) to write an application built using FreeRTOS running on a MicroBlze softcore processor, and am having issues trying to debug both the main source code and library source code simultaneously. I…
Joseph Hazel
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Will Vivado HLS arbitrary precision types support in XSDK?

I designed a function in HLS IPcore which process arrays of arbitrary precision types.I connected that core to the MICROBLAZE processor and generated Bitstream. I wrote C Codes in SDK to initialize HW IP core and to compile the codes. In TERA…
4am
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Opaque platgen failure in Xilinx EDK

This is running on: Ubuntu 64 LTS Xilinx Platform Studio 14.7 (lin64) I'm trying to run the microblaze_demo project included with the Virtex 5 board provided by PLDkit, but I'm getting a very unhelpful error. short error log Running XST synthesis…
Alex Raster
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Creating a custom pcore for Xilinx ISE 14.7?

A bit of a general question, but what is the most popular/common/easiest way of creating a custom pcore? I have seen some examples and they were mostly done on Matlab and since I do not have Matlab anywhere, I am a bit lost here. There has got to be…
Joe Carr
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variable does not properly update

Xilinx SDK 2016.1 freeRTOS823_xlinx OS platform My code seemed to work fine until I introduced some freeRTOS elements. The general functionality of my code as follows: In the Interrupt subroutine, I assign a value to a variable focusPosition that…
Nazar
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Unhandled fault when accessing AXIS FIFO registers through device driver

I am using a Zynq SoC with Petalinux 2016.2 I originally accessed my AXIS Fifo by opening it with open("/dev/mem", O_RDWR | O_SYNC) and using mmap to access it. I could access the registers of the AXIS device and interface successfully with the…
gavenant
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