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I'm using an Atlys Spartan6 xc6slx45. I have these errors when I run the program:

1. Check whether board is connected to the system properly.
2. In case of zynq board, check whether Digilent/Xilinx cable switch   settings are correct.
3. If you are using Xilinx Platform cable USB, ensure that status LED is green.

MicroBlaze is under RESET. Check if the Reset input to MicroBlaze and its  Bus Interfaces are connected properly
UNABLE to STOP MicroBlaze

File system.ucf:

#  Generic Template
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;
## Net fpga_0_clk_1_sys_clk_pin LOC=;
Net fpga_0_rst_1_sys_rst_pin TIG;
## Net fpga_0_rst_1_sys_rst_pin LOC=;

some details of the system.mhs:

PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ =    50000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST,  RST_POLARITY = 0

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_CLKIN_FREQ = 50000000
PARAMETER C_CLKOUT0_FREQ = 66666666
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 4.03.a
PORT CLKIN = CLK_S
PORT CLKOUT0 = clk_66_6667MHz
PORT LOCKED = Dcm_all_locked
PORT RST = Debug_SYS_Rst
END


BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 3.00.a
PORT Slowest_sync_clk = clk_66_6667MHz
PORT Ext_Reset_In = sys_rst_s
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Dcm_locked = Dcm_all_locked
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn_0
END

what value should I put for the reset to work the microblaze.

Classe Ensi E
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2 Answers2

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Digilent has reference design using microblaze you should loot at.

Otherwise, your UCF file doesn't have location constraint. Which pin is the clock? Which one is the reset? You have to tell the tool!

From the AC97 reference design, you should be fine if put these to the UCF (and remove everything else):

Net fpga_0_clk_1_sys_clk_pin LOC = "L15" | IOSTANDARD = "LVCMOS33";
Net fpga_0_rst_1_sys_rst_pin LOC = "T15" | IOSTANDARD = "LVCMOS33" | TIG;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;

You should notice that the microblaze system expected a 50MHz clock, while the clock you have on the board is 100MHz, you should make sure your system is still fine with this change. You also have to adjust your system.mhs appropriately.

Jonathan Drolet
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  • I don't understand what do you mean by this sentence "You should notice that the microblaze system expected a 50MHz clock, while the clock you have on the board is 100MHz, you should make sure your system is still fine with this change"??? – Classe Ensi E Apr 14 '15 at 20:37
  • In your .mhs and original .ucf, the clock is declared as a 50MHz clock. The clock on the board is 100MHz. You have to at least modify the .ucf (the code I gave has the modif) and .mhs to reflect the reality. I think EDK might deal with the change, but you may have to manually change the clocking ip with that change. – Jonathan Drolet Apr 14 '15 at 20:42
  • I changed the.ucf as you said and in .mhs I do this "CLK_FREQ = 100000000" but when I run the SDK I got the same error. – Classe Ensi E Apr 14 '15 at 21:10
  • Then I suggest you try the reference designs from Digilent and make sure your tools are setup properly. – Jonathan Drolet Apr 14 '15 at 21:12
  • PhysDesignRules:2449 - The computed value for the VCO operating frequency of PLL_ADV instance clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst is calculated to be 2000.000000 MHz. This falls above the operating range of the PLL VCO frequency for this device of 400.000000 - 1080.000000 MHz. Please adjust either the input frequency CLKINx_PERIOD, multiplication factor CLKFBOUT_MULT or the division factor DIVCLK_DIVIDE, in order to achieve a VCO frequency within the rated operating range for this device. – Classe Ensi E Apr 14 '15 at 21:44
  • Re-check your clock_generator_0 IP to make sure it's configured properly. – Jonathan Drolet Apr 14 '15 at 21:48
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I encountered the same problem. Since the problem is related to RESET, we should check the signal connected to the Reset pin of MicroBlaze core. This is from the mb_reset output pin of Processor System Reset IP (which is correct). From that core up, the reset signal of Processor System Reset is ext_reset_in which should have been connected to reset input signal directly. But I accidentally connect it to the ui_clk_sync_rst output pin of MIG, hence the error. Now I disconnect ext_reset_in from ui_clk_sync_rst and connect it to the input reset, and the problem is solved.

Xilinx makes changes oftentimes, making old design erroneous in current design tool. I am using Vivado/Vitis 2022.2.2 when I encountered this error, so I don't guarantee my solution works in the future version of Vivado/Vitis.

PS, another answer talks about clock. In current design tools, the clock into MicroBlaze (Clk) should be from ui_clk of MIG, instead of direct input clock sys_clk_i specified by xdc file (the frequency mismatches as mentioned in the answer). It is the case for all other IP cores automatically added.

zzzhhh
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