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Questions tagged [trust-zone]

For question related to implementing and interfacing TrustZone secure and normal world software and the monitor mode that brokers them.

Trustzone is an architecture to allow CPU sharing in cases where a traditional dedicated 'secure CPU' may have been used. This can reduce cost, power and board space.

A TrustZone ARM core has two virtual processors with a bus control 'NS' bit to provide hardware based access control. A TrustZone CPU can switch states between two worlds referred to as 'secure' and 'normal'. The worlds strive to be independent of each other requiring minimal changes to transition from a standalone OS/firmware system.

Memory, peripherals, BUS and CPU are made aware of the world via the 'NS' bit which allows the SOC to provide access control to secrets and code on the system. Master devices such as DMA, or multi-core devices can also be TrustZone aware or the bus master can be set to provide boot time locked access.

TrustZone solutions need several components,

  1. A TrustZone CPU
  2. A secure boot mechanism
  3. Bus control
  4. Secure world software

Reference:

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Trustzone: CPU0 non-secure and CPU1 Secure in

I am using zynq-7000(zed board) with A9 processor (dual core). I am trying to work with the Trustzone. I want to configure cpu1 to be running only in the secure world and cpu0 to be running a normal world application (petalinux). I read ug1019 and…
Khurram
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code after vector table ARM A9

I am implementing a small OS as a university project in a A9 chip (a Xilinx Zynq). I am using trustzone to implement some features and I want to pass through SVC calls from user mode directly to monitor, so I issue an SMC in my SVC handler. Here it…
josecm
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What prevents any malcious software from raising SMC exception in ARM TrustZone?

I am reading about ARM TrustZone. I read that when the Normal World wants a function from the Secure World, they raise SMC exception which makes a transfer to the Secure World. The thing that I did not understand is what prevents any malicious code…
DigitalPerson
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How does Linaro schedule OPTEE?

I want to know which part of the code is the scheduler of project OPTEEhttps://github.com/OP-TEE. More specifically, the code decides that on which CPU secure world and normal word processes are running for multicore architecture. Any advice is…
S.Wan
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How to Introspect normal world from secure world using TrustZone?

I have learned that secure world can protect critical data from being accessed by normal world, What I don't understand is that how do I measure the integrity of normal world from secure world. I find some relevant work in the Samsung TZ-RKP and…
Tgn Yang
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what is a simple way to implement ARM SMC

I am trying to write a program that issues one SMC call. After searching the previous questions, it is my understanding that there is no real API within the Linux kernel for implementing ARM SMC? I am working on a prototype based on msm8974, and…
user3326293
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Trust Zone on Raspberry Pi unexpected behaviour?

I am working on the trust zone extension on raspberry pi B+ which has the ARM1176JZF-S processor. According to given documentation on arm11, there will be 3 exception vector tables each for Secure world, Non-secure(NS) world and monitor mode resp.…
AvK
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Easiest way to access secure (TrustZone) instructions from privileged context on Cortex A8/DM3730

I have a pretty weird thing I need to do: Access some "secure" instructions for things that don't really need to be done in a secure context. In short: I need to get in to Secure Mode, but not because I want Hardware TPM-ish functionality or…
user770901
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How are Trustzone Components used in i.MX53?

Can anyone explain how TZ technology is enabled in I.MX53 ? I am totally confused since internet says i.MX53 board has Trustzone enabled but all i can find is an interrupt controller in it. Where are the rest of the components as given in…
Paarth
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ARM Trustzone memory aliasing

I am trying to understand the ARM Trustzone implementation and came across the memory aliasing wherein the same memory is interpreted as secure and non-secure based on the 33rd bit of that address. I am not able to understand the concept of memory…
srikanth mucharla
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ARM TrustZone-M secure world variable shadows nonsecure variable?

I have an application written for an STM32-L552ZE Cortex M-33 based MCU which makes use of TrustZone-M. Both worlds have a main.h, main.c and both wolds' header files declare a variable foo (i.e. both the secure main.h and nonsecure main.h declare…
iMrFelix
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ARM TrustZone: Accessing a non-secure buffer from a secure monitor runtime service

My setup consists of a STM32MP157C-DK2 which uses Trusted Firmware-A to load SP-MIN as BL32 and uBoot+Linux as BL33. I am trying to get a small example working where I create an SMC from the Linux Kernel which passes a reference to non-secure…
TNTea
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Cortex-M33 MTB configuration - When MTB buffer is full

I am exploring the MTB feature on Cortex-M hardware and doing experiments on Arm mps2+ FPGA board with the Cortex-m33 image, which enables the TrustZone technique. From what I learned, the MTB can be configured to record non-sequential branches of…
Xi Tan
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How to get a UTC timestamp in OP-TEE Trusted Application (TA) in datetime format?

Disclaimer: It took me a solid 4-5 hours of looking for an answer and after figuring it out I decided to post it here for people in the same place. OP-TEE is quite a good environment to develop TAs and CAs, however, there is no straightforward…
Everyone
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sequence flow from non-secure to secure

I want to be sure if I understand the process describe non-secure high level os sending smc command. According to Arm user manual and many blogs and articles, I think this is the following scenario: EL0(non-secure) to EL1(non-secure) -…
sivandahan
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