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Questions tagged [trust-zone]

For question related to implementing and interfacing TrustZone secure and normal world software and the monitor mode that brokers them.

Trustzone is an architecture to allow CPU sharing in cases where a traditional dedicated 'secure CPU' may have been used. This can reduce cost, power and board space.

A TrustZone ARM core has two virtual processors with a bus control 'NS' bit to provide hardware based access control. A TrustZone CPU can switch states between two worlds referred to as 'secure' and 'normal'. The worlds strive to be independent of each other requiring minimal changes to transition from a standalone OS/firmware system.

Memory, peripherals, BUS and CPU are made aware of the world via the 'NS' bit which allows the SOC to provide access control to secrets and code on the system. Master devices such as DMA, or multi-core devices can also be TrustZone aware or the bus master can be set to provide boot time locked access.

TrustZone solutions need several components,

  1. A TrustZone CPU
  2. A secure boot mechanism
  3. Bus control
  4. Secure world software

Reference:

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set bandwidth API purpose

According to the following change: qseecom: Add API to set bandwidth for CE HW Want to understand what is CE clk ? What is it responsible for ? Thanks,
sivandahan
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`cmse_check_address_range` changes behaviour with compiler upgrade

I'm using a Cortex-M33 with arm trust-zone. I have a secure api inside my secure firmware that I can call from my non-secure firmware. All works as expected - at least until I upgraded my compiler from gcc-arm-none-eabi-7-2018-q2-update to…
kratenko
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How is working the process of direct access to memory in non-SecureOS and SecureOS in trustzone systems

Im not sure if I understand the full flow of CPU direct access to memory in ARM processors, I interested to know which part of memory access the cache (L1 and L2) ,DMA and MMU(or secure MMU) are participate. I'm not sure if I understand the process…
scofield
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How do I know whether ARM Trustzone is in use or not?

I have a testboard, CPU is A72. I see that A72 supports Trustzone, but how do I know whether Trustzone is in use or not? Thanks.
Smith
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How to use an ARM Secure Monitor Call (SMC)

I am running an Operating System that uses a ARM Cortex processor on a FPGA. To be able to access this region of memory on this board, I need to be running a secure world. I was told I need to use a Secure Monitor call to enter a secure world. If I…
Chris
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Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"?

I've gotten virtual memory working on ARMv8 after crafting the page tables. Oddly, most of my translations are working (identity mapped) save for Flash which sits at physical address zero. I use a single function that edits the page tables, so the…
sherrellbc
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TrustZone vs ROM as root-of-trust in Secure Boot

A lot of literature that I stumbled upon referred TrustZone as a mechanism that facilitates Secure Boot (as can be seen here, and a lot more). To my knowledge, Secure Boot operates this way: "Root-of-Trust verifies img1 verifies img2 ..." So in…
user3848844
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Strange behavior using goto for error handling in C

I am developing a basic application in C, using the OP-TEE (TrustZone Secure OS) libraries. I am running the code in QEMU. Here is the code in which the strange behavior occurred: void prepare_rsa_operation(TEE_OperationHandle *handle, uint32_t alg,…
Dalton Cézane
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Implementation of optee trust os on raspberry pi 3

I am trying to implement OP-TEE trust OS on Raspberry Pi 3, with a Raspbian OS. The OP-TEE website mentions that it supports both 32 bit and 64 bit architectures, but when I tried to implement, it is automatically runs aarch64 make files which aint…
Varsha Satish
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Setting timer/counter in the Arm TrustZone

My goal is to set a counter/timer in the secure world that cannot be disabled from the normal world. When the timer expires, it raises an interrupt that will be handled by the secure world. Is it possible? UPDATE: I have found OP TEE os project…
Fardin Abdi
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IMX53 initialize stacks

I am booting Android on an IMX53 Sabre tablet. I am trying to initialize stacks for the different processor modes. The following is my monitor initialization code: @ Install Secure Monitor @ ----------------------- ldr r1, =ns_image …
rijurekha
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IMX53 external abort

I am booting Android on an IMX53 Sabre tablet. The last few lines seen on serial port as android boots up normally is as follows: warning: `rild' uses 32-bit capabilities (legacy support in use) pmem: request for physical address of pmem region from…
rijurekha
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Persistence of Android KeyStore and access permissions to key material

How persistent is the Android KeyStore, whether hardware-backed (via TrustZone) or not? Do the keys that are generated within the KeyStore get deleted after the creating app is uninstalled? Do they also get deleted upon a factory reset? (especially…
user1118764
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Are Android hardware backed credential storage wiped upon factory reset?

I'm interested in storing data in hardware backed storage(in TrustZone) as described in https://developer.android.com/about/versions/android-4.3.html. Do these survive a factory reset? Thanks.
user1118764
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arm trustzone monitor mode switch design

the basic world switch flow is: set FIQ to monitor mode normal world -> FIQ triggered -> enter monitor mode (do switch to Secure world, restore Secure world context) -> in Secure world sys mode -> FIQ is not clear, enter FIQ handler in Secure…
user487363
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