2

I am working on the trust zone extension on raspberry pi B+ which has the ARM1176JZF-S processor. According to given documentation on arm11, there will be 3 exception vector tables each for Secure world, Non-secure(NS) world and monitor mode resp. And c12 register will hold the base address of both secure and NS world exception vector table base addresses.

I added both these addresses to the c12 register in their corresponding worlds(Secure / NS). I tried SWI (svc) in both worlds. I found that it is working fine in secure world but in the NS world the control goes to the NS reset handler for a SWI instead of SWI handler. I used the following commands :

For secure world :
    LDR r0, =_start //_start - base address of secure vector table
    MCR p15, 0, r0, c12, c0, 0
For Non-secure World :
    LDR r0, =_ns_start //ns_start - base address of non-secure vector table
    MCR p15, 0, r0, c12, c0, 0

Here is my code : https://github.com/avk7vk/arm_bare_metal/tree/master/trustzone-smc

Please let me know the issue here .

AvK
  • 75
  • 1
  • 9
  • The bottom 5 bits of the Vector Base Address Register are ignored, so you need to ensure the vector table is 32-byte aligned. – unixsmurf Nov 09 '14 at 09:18

1 Answers1

1

The Vector Base Address Register (VBAR) has the bottom five bits defined as "res0", meaning they will be ignored and treated as zero. As a result, your vector table must be 32-byte aligned. Achieved with:

    .align 5
_ns_start:
    ldr pc, ns_Reset
    ...
unixsmurf
  • 5,852
  • 1
  • 33
  • 40