Questions tagged [thumb]

A reduced instruction set for ARM processors (based on a 16-bit encoding, instead of 32 bits in standard ARM mode), originally intended for embedded systems with a small amount of RAM. Also for question with the later Thumb2 mixed 16 and 32 bit instruction modes. Consider the tags 'slider' and 'thumbnails' for other meanings of 'thumb'.

This tag is for questions concerning the ARM CPU's operating mode called thumb. Questions about thumb assembly language, interworking between thumb and ARM mode as well as operating system issue in dealing with thumb mode are on topic.

The Thumb instruction set (16 bit only) with restricted use of r8-r15 was later extended to include a mix of 16 and 32 bit instructions. This was called Thumb-2. Thumb-2 is a marketing term. Different CPU families and even specific devices have different instructions. Thumb-2 is fairly meaningless in a technical sense (except it means variable length instructions (always two halfwords) are available along with 16 bit thumb instructions). Thumb-2 at wikipedia

On modern ARM CPUs, Thumb-2 is as rich as the traditional 32-bit mode and much more memory efficient.

For questions related to the scrollbar thumbs consider one of,

For questions about thumbnails, use the tag .

See also:

The paper Profile guided selection of ARM and thumb instructions gives some benchmarking of legacy thumb versus 32 bit modes. Different algorithms are faster in one mode versus the other. The paper is somewhat obsolete as Thumb-2 will be more efficient in modern (2014+) CPUs. Although some deeply embedded devices may only support Thumb.

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ARM (thumb) firmware mod...how to turn few lines of ASM to code to make a mod

Have firmware disassmbled with IDA (ARM920 Core).. most is Thumb mode....some is ARM mode Want to make some mods, in ASM. What is the easiest way to turn few lines of ASM (well few dozen) into machine language. Can some one suggest a FREE tool /…
vmanta
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How to Properly Handle the LR Register in an Interrupt Service Routine for Thumb Mode on ARM?

When ARM chips(cortex-A7)are compiled in thumb mode, the program may run abnormally, and the exception point has been located. The problematic C code is: while (locked && result) { // while loop body } The assembly code compiled from the…
xukai
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Vldm arm instruction

ptr_arr .req R1 // alias .type new332, %object .align 2 new332: .word 12198,1291, -2198219 .... //255 numbers .size new332,.-new332 ldr ptr_arr, =#new332 // new332 is a array of integers vldm…
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How to get qemu to run an arm thumb binary?

I'm trying to learn the basics of ARM assembly and wrote a fairly simple program to sort an array. I initially assembled it using the armv8-a option and ran the program under qemu while debugging with gdb. This worked fine and the program…
Nathan S
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ARM Thumb extra POP and BX in epilogue

I disassembled some object files for an embedded target to inspect the code size, and noticed a peculiarly "asymmetric" prologue-epilogue pair. It began with a push for 4 registers including lr, and ended with a pop of 3 registers, followed by a pop…
Mona the Monad
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Can't replace MOVW / MOVT with LDR

I want to replace this movw / movt combination with a single ldr instruction: movw r0, #0x3800 movt r0, #0x4002 | V ldr r0, =0x40023800 However, after this change the code no longer works. Since this is the only part I changed, it…
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Dynamic assembly in THUMB or ARM mode

In GNU AS I understand it's possible to use Unified Syntax and sometimes get ARM code to automagically compile as Thumb code. In some cases this can produce impressive gains in code density and in many cases it just doesn't work because there's some…
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How do interrupted instructions get continued with Cortex-M NVIC?

(I am learning the Cortex-M microcontroller and can't help compare it to the x86 cpu.) With x86, for a fault, such as page fault, the instruction that caused/triggered the fault will be executed again after the fault has been handled. But with ARM…
smwikipedia
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Ordering of registers in PUSH and POP brackets

ARM documentation says the following for PUSH and POP PUSH stores registers on the stack, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address. POP loads registers from…
KMC
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ARM Thumb BL instruction loops to itself

I'm trying to assemble this code using Keystone and execute it with the Unicorn engine: start: add r0, r0, #1 add r1, r1, #2 bl start b start In my opinion, the bl instruction should save the address of the next instruction to the…
ForceBru
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ARM assembly recursive sum of 1..n

So I've had the following task that needs to be written in ARM Assembly Please test the subroutine by passing the value of n equals 5. The result should equal 15. If n equals 3, the result is 6. I was given the corresponding Java code: int sum…
Sikablato
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How is "!" part of "LDM R1! {R2}" instruction in Armv6-M Architecture Encoded?

When I look at the official Arm specifications, ! Causes the instruction to write a modified value back to . If ! is omitted, the instruction does not change in this way. This is how the function is explained, yet the ASL Code is as…
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How can I save the call stack from an exception handler in Cortex M4?

Here is what I want to achieve: Whenever I receive a hard fault or watchdog interrupt, I will save the previous instruction's address to some RAM location that will survive a reset. Kinetis M64 watchdog gives me 256 CPU cycles before it issues the…
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How do I optimise a filter loop for Cortex-M3?

I just need to alter the code so that it does the same basic function but more optimised, basically I think the filter loop is the main piece of code that can be changed as I feel there are too many instructions in there, but don't know where to…
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How do I divide by 8, using ARM Assembly Code?

I have to complete the program framework below to calculate the sum of only those values in the data area divisible by 8 and store the result in register r5. My program must be able to work for any number of data values (within memory and 32-bit…
Hysteria103
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