A package for using Python as a hardware description and verification language. Although it cannot be synthesized directly into hardware, MyHDL code can be automatically translated to Verilog or VHDL, and synthesized with existing HDL development tools.
Questions tagged [myhdl]
34 questions
1
vote
0 answers
MyHDL free variables
Whenever I try to call this function in the MyHDL implementation of MD5 I've been working on I get this error:
File "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_misc.py", line 149, in raiseError
raise ConversionError(kind, msg,…
A Gomez
- 11
- 1
1
vote
1 answer
python myhdl package how to generate verilog initial block
From the code mostly from the sample of myhdl:
from myhdl import Signal, intbv, delay, always, now, Simulation, toVerilog
__debug = True
def ClkDriver(clk):
halfPeriod = delay(10)
@always(halfPeriod)
def driveClk():
clk.next =…
minghua
- 5,981
- 6
- 45
- 71
1
vote
2 answers
Output port missing in generated Verilog code from MyHDL
I am trying to generate a verilog module from the following MyHDL module:
top.py:
from myhdl import *
from counter import Counter
def Top(clkIn, leds):
counter = Counter(clkIn, leds)
return counter
clkIn = Signal(bool(0))
leds =…
nijoakim
- 930
- 10
- 25
1
vote
1 answer
MyHDL VHDL conversion: no index value can belong to null index range
For an algorithm I implemented and successfully converted to VHDL, I get this error during the "Static elaboration of top level VHDL design":
no index value can belong to null index range
I boiled the code down to the essential part (you might…
JoVaRi
- 80
- 8
1
vote
1 answer
Dynamic Instantiation: How to dynamically wire interfaces in myHDL
I'm trying to make a python library for dynamically making a UART interface between a PC and FPGA using pySerial using myHDL 1.0dev
It takes names for datatypes and their properties, and instantiates a RAM block, as well as allow access to…
Enrique Mendez
- 131
- 4
1
vote
1 answer
myhdl constraints associating multiple pins to a variable
I will be using an iCE40HX8K
given the evaluation boards constraint file
set_io LED3 A2
set_io LED7 B3
...
etc
whats the best way to bundle all 8 LED's into one variable
I had trouble associating things with my constraint file and ended up…
Chris Camacho
- 1,164
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- 31
1
vote
2 answers
yield statement in myhdl
I have the following code in my myhdl environment:
def rst(self):
rst.next=rst.active
self.wait_clks(5)
def wait_clks(self, cycles):
for _ in range(cycles):
yield self.clk.posedge
the above code doesn't work but when I replace it…
user3293692
- 567
- 1
- 5
- 14
1
vote
1 answer
AlwaysError when running a testbench on a synchronizer
I encountered this error when running a testbench, together with a synchronizer built on two existing D-FFs.
File "/home/runner/design.py", line 28, in Sync
@always_seq(clk.posedge, reset=reset)
File…
user3663339
- 33
- 2
1
vote
0 answers
siir.py unable to run
I tried Chris Felton's myHDL sample code.
I could not get the Simulation module imported functions to compile with the following errors:
Traceback (most recent call last)
File "siir.py", line 497, in
tb = flt.TestFreqResponse(Nloops=3,…
user3555884
- 11
- 2
1
vote
1 answer
Why does this example from the myHDL manual give me different results?
Here is an example that I've copied from the myHDL manual. In my code the generator FSM() never gets invoked so the state is always 'SEARCH'.
I can't figure out why the generator is not getting called.
Edit:
Changing this line from:
reset =…
rupello
- 8,361
- 2
- 37
- 34
1
vote
1 answer
AST compilation errors on basic examples from myHDL manual in iPython notebook
Edit: This only happens when I run the code from inside iPython notebook. It works fine from a regular .py file
I'm just getting started with learning myHDL and I'm getting compilation errors using @instance or @always_comb generators like…
rupello
- 8,361
- 2
- 37
- 34
1
vote
1 answer
HDL sythesis complains about missing signals in sensitivity list
Hello I've got this simple VHDL process (Generated from MyHDL code):
DIGIPOT_CONTROLLER_CONNECTCLOCK: process (delayedClock) is
begin
if to_boolean(clkEn) then
if to_boolean(delayedClock) then
scl_d <= '0';
else
…
Bruno Kremel
- 125
- 3
- 14
0
votes
0 answers
Is there a more terse way to create a group of empty lists?
I can declare a bunch of empty lists as:
a,b,c = [],[],[]
or
a,b,c = [0]*16,[0]*8,[0,1,2]
Is there a more concise way to declare a bunch of lists?
(I have also used list comprehensions, and dedicated classes to do it, and am just looking for a more…
user3761340
- 603
- 5
- 19
0
votes
1 answer
I need to convert this VHDL code to MyVHDL Python, how to?
i need to convert this code to myhdl in python for my school work, anyone can help me?
library ieee;
use ieee.std_logic_1164.all;
entity simple_example is
port (
a : in std_logic;
b : in std_logic;
o : out std_logic
…
Guilherme Engel
- 3
- 1
0
votes
2 answers
MyHDL: Unary XOR
How to write myhdl code to implement Unary XOR in verilog
reg [63:0] large_bus;
wire xor_value;
assign xor_value = ^large_bus;
doesn't work for me.
@block
def dataVecXor(large_bus, xor_value):
@always_comb
def outputlogic():
…
Abhisheietk
- 160
- 5