A package for using Python as a hardware description and verification language. Although it cannot be synthesized directly into hardware, MyHDL code can be automatically translated to Verilog or VHDL, and synthesized with existing HDL development tools.
Questions tagged [myhdl]
34 questions
0
votes
1 answer
What's the recommended MyHDL design pattern for multi-tick operations?
I'm trying to learn MyHDL by writing a very simple machine with just a handful of instructions and operations. What I'm struggling with is the best way to design my machine to handle operations that take multiple clock cycles to resolve. Currently,…
Nick
- 53
- 7
0
votes
2 answers
How to make MyHDL generate variable with arbitrary width in process?
I would like to do a sum of signals that I have in a list, naturally I have used variable and for (as I would in VHDL):
@always_comb
def sum():
sum = 0
for i in range(len(summands)):
sum = sum + summands[i]
…
Bruno Kremel
- 125
- 3
- 14
0
votes
1 answer
MyHDL: Object type is not supported in this context
I'm trying to convert this code to Verilog:
from myhdl import always_comb
from myhdl import modbv
from myhdl import Signal
from myhdl import concat
from myhdl import toVerilog
var0 = modbv(15)[12:]
var1 = modbv(15)[12:]
var2 = modbv(15)[12:]
var3 =…
Angel
- 360
- 6
- 13
-2
votes
1 answer
Why multiple HCL languages
I understand that Chisel is a HDL/HCL language to overcome some of Verilog/SystemVerilog restrictions by using higher abstraction level.
And it is open source as well.
It might be a bit naive and presumptuous, but still I would like to ask.
My…
Navnish Garg
- 103
- 7