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Questions tagged [msr]

MSR (Model-Specific Registers) are registers inside the CPU that provide direct access to advanced CPU features.

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Hardware Processor Counters Incorrectly Resetting

I wrote a program which reads the APERF/MPERF counters on an Intel chip (page 2 on http://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-software-developer-vol-3b-part-2-manual.pdf). These counters are readable/writable via the…
Shookit
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Unable to disable the hardware prefetcher

I am trying to disable the hardware prefetcher to run some memory benchmarks on an Intel core i5 2500. The problem is that there is no option whatsoever in my BIOS to enable or disable the prefetcher. So I am trying to use msr-tools to disable the…
Thejasvi MV
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Converting rdpmc_reference_cycles to 64-bit in MASM

I've been using the following code in assembly language to read performance-monitoring counters using the RDPMC instruction: rdpmc_reference_cycles proc mov ecx, 1h shl ecx, 30 add ecx, 2 xor eax, eax xor edx, edx rdpmc …
daniel
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Setting Package-Wide MSRs for Uncore Frequency and Cache Allocation Technology

I am trying to set way masks for different class of service (COS) on an Intel Xeon processor. I am using the following command to make COS0 use all but the last four cache ways: sudo wrmsr 0xc90 0x7f0 If I rdmsr the 0xc90 on processor 0 I find that…
Tez_Nikka
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How to download Slack history messages if you are not the app admin?

I am trying to download the history messages for a specific Slack app, let's say MLflow. I found a few open-source tools on Github but none of them actually work for me. It seems that slack has disabled ways for non-admin to create the access token…
Jimmy Zhao
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Qemu : tracing msr read/write

Qemu does have some tracing facilities listed in trace-events-all. However, there is no keyword to figure out when Model Specific Registers are read or written. Is there any workaround about this?
Mahouk
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How to make changes to msr 0x199 from EFI stick?

I have a macbookpro11,3 without a battery. When battery is removed the firmware throttles the CPU to half speed. In Windows I can override this using Throttlestop to turn off BD PROCHOT and set multiplier to 25. I want to do this from EFI so that…
lx07
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I write a c code with inline assembly code to read msr, but failed

I use following code to read msr, but it crashed when running. I don't know why. #include #include int main() { register long ecx asm("%ecx"); register long eax asm("%eax"); register long edx asm("%edx"); …
Larry.L.Li
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wrsmr command doesn't register my input in MSRs

I have the following environment: ubuntu 12.04 kernel 3.2.0-29-generic-pae all installed on parallels version 11.0.1. I have installed msr-tools using apt-get command. My problem is when I execute the following command that is supposed write a value…
VahidMLA
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LBR for large programs

The Last Branch Record feature in Intel processors. Are they suitable for large programs that have a lot of branching? If yes how do you manage to find the entire path by just using 16 MSR registers incase of Haswell?
Questioner
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How to avoid MSR reset after calling system call

My purpose is to measure counts of different performance events of particular application using model specific registers (MSRs). Since, this can be done by using RDMSR and WRMSR at ring 0,I have used Linux module to call these instructions and…
pramod parbhankar
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Is there a way to identify the instruction that caused the most recent Last Level Cache miss on modern Intel processors?

I am currently able to read hardware counters on the Last Level Cache misses and references from user space using wrmsr to select them and then rdpmc to read them. However, while some of the misses are very obvious references that I would not to…
merlin2011
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Modifying machine registers for AMD machines

I was looking into modifying MSRs and PCI configuration registers on AMD machines. I know which bits to change etc by looking into this: http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/42301_15h_Mod_00h-0Fh_BKDG1.pdf I tried using…
user2155669
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how to reset general purpose performance counter of intel

I know we can use wrmsr and rdmsr instruction to set the performance counter and read the general purpose performance counter register. However, my question is: Do we need to reset the general purpose performance counter register before we issue…
Mike
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What are the conditions to read MSR MPERF?

I'm trying to read the MPERF and APERF MSRs. However, when I do so, the machine reboots, probably because of a GP exception. Here is the code I use: ; Read MPERF register mov ecx, 0xe7 rdmsr The code breaks on rdmsr. I have an Intel Haswell…
Baptiste Wicht
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