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Questions tagged [msr]

MSR (Model-Specific Registers) are registers inside the CPU that provide direct access to advanced CPU features.

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IA32 vs MSR prefix for x86 MSR names

Intel sometimes uses the MSR_ prefix for MSR names, and sometimes IA32_, even for the same MSR. For example, on SNB, in SDM Volume 4, they document both IA32_PERF_STATUS and MSR_PERF_STATUS for MSR 0x198 with somewhat different (but not exactly…
BeeOnRope
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Correctly disable Hardware Prefetching with MSR in Skylake

I am trying to disable hardware prefetching on my machine: CPU family: 6 Model: 78 Model name: Intel(R) Core(TM) i5-6200U CPU @ 2.30GHz I have checked with: gcc -march=native -Q --help=target|grep march - command and…
Ana Khorguani
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Perf Error: The sys_perf_event_open() syscall returned with 22 (Invalid argument) for event (msr/tsc/)

I am using perf to monitor the system for certain events. However, I get the following error and I have no idea where it comes from,as the event is listed in perf list sudo perf record -e msr/tsc/ -a Error: The sys_perf_event_open() syscall returned…
assembly_question
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Precise measurements of maximum cycle count with RDTSC

I'm developing low level routines for binary search in C and x64 assembly, and trying to measure the exact execution time for searches of uncached arrays (data in RAM). Searching the same array for different targets takes widely varying amounts of…
Nathan Kurz
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How to execute a piece of kernel code on all CPUs?

I'm trying to make a kernel module to enable FOP compatibility mode for x87 FPU. This is done via setting bit 2 in IA32_MISC_ENABLE MSR. Here's the code: #include #include #include #include…
Ruslan
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How to measure energy consumption of a process in linux without any external hardware meter?

I had tried googling for it and had found MSR_PKG_ENERGY_STATUS under RAPL but unfortunately it has support for only newer processors like Sandy Bridge, Ivy Bridge etc. Is there any other way to get it in older processors? This is my processor :…
Saravanan Setty
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MSR vs MMIO/PCIe configuration space

Intel sometimes uses MSRs and sometimes "internal" PCIe devices to expose configuration options to the OS. I could not find any ressources which describe the advantages/reasons for using PCIe devices over MSRs. Since the MSR space is 2^32 there…
Benedict Schlüter
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wrmsr instruction causing triple fault in bootloader while trying to enable paging?

I am working on an OS and am trying to transition into long mode in order to execute 64-bit Rust code in an x86_64 environment. boot.asm: ;;;;;;;;;;;;;;;;;;;;;;;;; ; STAGE ONE / BOOT SECTOR ;;;;;;;;;;;;;;;;;;;;;;;;; [ORG 0x7c00] ; this doesn't work…
TheTetrisDude
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Reading CPU temperature with assembly

Hi i was wondering how could i read the CPU's temperature. I tried putting 0x19C in the ECX register and then calling rdmsr (to get IA32_THERM_STATUS) but the destination registries (EDX:EAX) are empty. I am using Pure64 operating system.
NICOLAS FRANCO RAMPOLDI
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value of PMC (Performance Monitoring Counter) for L3 cache-misses is too high

I'm searching a way to estimate the number of L3 cache-misses by using 'IA32_PERFEVTSELx' and 'IA32_PMCx' MSR pair on my Linux PC with Intel CPU (Intel i7 6700 skylake). To do that, I installed a timer in the kernel and it reported the value of a…
nickeys
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How to check msr.le at runtime using built-ins?

This question came up in a Power8 in-core crypto patch. The patch provides AES using Power8 built-ins. When loading a VSX register we need to perform a 128-bit endian reversal when running on a little-endian machine to ensure the VSX register loads…
jww
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Intel PMU: Setting overflow flags in IA32_PERF_GLOBAL_STATUS register

I need to set an overflow flag (e.g. bit #33) in IA32_PERF_GLOBAL_STATUS MSR, which is read-only. On Skylake (which supports architectural performance monitoring version 4) it's easy, because there is IA32_PERF_GLOBAL_STATUS_SET MSR available for…
Ilya Verbin
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how to enable linux perf tool's branch sampling

I use linux perf tool to collect branch info of programs, and the command and result is as follow: $ sudo perf record -b /bin/ls Error: No hardware sampling interrupt available. No APIC? If so then you can boot the kernel with the "lapic" boot…
e_ahrea
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How do I write x86 Debug registers from user space on OSX?

I'd like to play around with the debug MSRs defined in the x86 spec (DR0-7) from my OSX user-space program. Unfortunately, these require CPL == 0 (aka ring 0). I've thumbed through the OSX syscalls and with the exception of kernel_debug nothing…
nall
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Write/Read AMD geode LX800 CPU EEPROM

I have read in AMD geode LX800 CPU datasheet (http://goo.gl/fUl5RM) that this CPU have in Security Block an internal EEPROM that can be used to store user data. I can read and write MSR registers using linux, but i dont now how to access eeprom…
frico
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