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Questions tagged [intel]

For issues related to Intel semiconductor chips and assemblies, Intel architectural features and ISA extensions, and Intel chips micro-architecture.

Intel Corporation is an American multinational semiconductor chip maker corporation headquartered in Santa Clara, California, United States. Intel is the inventor of the x86 processor architecture and makes central processing units, motherboard chipsets, graphic processing units, network interface controllers and much more devices related to communications and computing.

In addition to their hardware offerings Intel also produces a variety of software including compilers, libraries for mathematical computation(Intel MKL), threading(OpenMP, Intel Performance Primatives, Threading Building Blocks), parallel communication(MPI,OFED/True Scale Infiniband Stack) and several other products included in the Intel Parallel Studio toolkit. In addition to these offerings which are widely used in HPC Intel also produces software for datacenter management and is one of the most prolific contributors to the Linux kernel.

This tag should be used for questions about Intel hardware and software.

The x86 and/or x86-64 tags are better choices for questions about assembly programming for the architecture, rather than things like performance tuning specifically for Intel's implementation of x86.

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How does CLFLUSH work for an address that is not in cache yet?

We are trying to use the Intel CLFLUSH instruction to flush the cache content of a process in Linux at the userspace. We create a very simple C program that first access a large array and then call the CLFLUSH to flush the virtual address space of…
Mike
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Enabling intel virtualization (VT-X) without option in BIOS

Sorry if the question is already answered, but I haven't found answer for my particular situation, that is a little different. I'm installing all the tools necessary for android programming. I have created an android virtual device, but the problem…
Carlos
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How to transpose a 16x16 matrix using SIMD instructions?

I'm currently writing some code targeting Intel's forthcoming AVX-512 SIMD instructions, which supports 512-bit operations. Now assuming there's a matrix represented by 16 SIMD registers, each holding 16 32-bit integers (corresponds to a row), how…
lei_z
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Strange JIT pessimization of a loop idiom

While analyzing the results of a recent question here, I encountered a quite peculiar phenomenon: apparently an extra layer of HotSpot's JIT-optimization actually slows down execution on my machine. Here is the code I have used for the…
Marko Topolnik
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Is the Intel Xeon Phi usable without a costly Intel Compiler?

Does the Intel Xeon Phi coprocessor, to be usable as parallel platform, require a license of the Intel Composer XE compiler, or are there alternative compilers?
clstaudt
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Why is it not possible to push a byte onto a stack on Pentium IA-32?

I've come to learn that you cannot push a byte directly onto the Intel Pentium's stack, can anyone explain this to me please? The reason that I've been given is because the esp register is word-addressable (or, that is the assumption in our model)…
Tim Green
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Loop unrolling to achieve maximum throughput with Ivy Bridge and Haswell

I am computing eight dot products at once with AVX. In my current code I do something like this (before unrolling): Ivy-Bridge/Sandy-Bridge __m256 areg0 = _mm256_set1_ps(a[m]); for(int i=0; i
Z boson
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Why are Intel x87 registers 80 bits wide?

Why is such a “weird” register size used? Is there any documentation on why it is not preferable to use 64 or 128 bits for those registers?
JohnTortugo
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C++/compilation : is it possible to set the size of the vptr (global vtable + 2 bytes index)

I posted recently a question about the memory overhead due to virtuality in C++. The answers allow me to understand how vtable and vptr works. My problem is the following : I work on supercomputers, I have billions of some objects and consequently I…
Vincent
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Memory alignment on a 32-bit Intel processor

Intel's 32-bit processors such as Pentium have 64-bit wide data bus and therefore fetch 8 bytes per access. Based on this, I'm assuming that the physical addresses that these processors emit on the address bus are always multiples of 8. Firstly, is…
G S
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_mm_load_ps vs. _mm_load_pd vs. etc on Intel x86 ISA

What's the difference between the following two lines? __m128 x = _mm_load_ps((float *) ptr); __m128 y = _mm_load_pd((double *)ptr); In other words, why are there so many different _mm_load_xyz instructions, instead of a generic __m128…
user541686
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assembly registers esp and ebp

I am currently learning assembly for Intel processors. Since the stack 'grows down', why do we have to add in order to access a specific element [ebp + 8] ;; This will access the first param I konw we have to skip the old ebp value and the return…
Andrei
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Why can't my ultraportable laptop CPU maintain peak performance in HPC

I have developed a high performance Cholesky factorization routine, which should have peak performance at around 10.5 GFLOPs on a single CPU (without hyperthreading). But there is some phenomenon which I don't understand when I test its performance.…
Zheyuan Li
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Is there a complete x86 assembly language reference that uses AT&T syntax?

Ideally there would be a version of Intel's Software Developer's Manuals written in AT&T syntax, but I would be happy to find anything that is close enough.
sigjuice
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Will runtimes like CLR and JVM be able to use Haswell TSX instructions?

After reading Anandtech on 'Haswell TSX' (tranactional memory barriers) I immediately wondered if CLR/JVM will be able to make use of these in C#/Java/Scala/F# for heavily parallel applications (C# Rx/TPL/TFD).
yzorg
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