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Questions tagged [intel]

For issues related to Intel semiconductor chips and assemblies, Intel architectural features and ISA extensions, and Intel chips micro-architecture.

Intel Corporation is an American multinational semiconductor chip maker corporation headquartered in Santa Clara, California, United States. Intel is the inventor of the x86 processor architecture and makes central processing units, motherboard chipsets, graphic processing units, network interface controllers and much more devices related to communications and computing.

In addition to their hardware offerings Intel also produces a variety of software including compilers, libraries for mathematical computation(Intel MKL), threading(OpenMP, Intel Performance Primatives, Threading Building Blocks), parallel communication(MPI,OFED/True Scale Infiniband Stack) and several other products included in the Intel Parallel Studio toolkit. In addition to these offerings which are widely used in HPC Intel also produces software for datacenter management and is one of the most prolific contributors to the Linux kernel.

This tag should be used for questions about Intel hardware and software.

The x86 and/or x86-64 tags are better choices for questions about assembly programming for the architecture, rather than things like performance tuning specifically for Intel's implementation of x86.

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What was the original reason for the design of AT&T assembly syntax?

When using assembly instructions on x86 or amd64, programmer can use "Intel" (i.e. nasm compiler) or "AT&T" (i.e. gas compiler) assembly syntax. "Intel" syntax is more popular on Windows, but "AT&T" is more popular on UNIX(-like) systems. But both…
antonone
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How exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistent

This loop runs at one iteration per 3 cycles on Intel Conroe/Merom, bottlenecked on imul throughput as expected. But on Haswell/Skylake, it runs at one iteration per 11 cycles, apparently because setnz al has a dependency on the last imul. ;…
Peter Cordes
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How are x86 uops scheduled, exactly?

Modern x86 CPUs break down the incoming instruction stream into micro-operations (uops1) and then schedule these uops out-of-order as their inputs become ready. While the basic idea is clear, I'd like to know the specific details of how ready…
BeeOnRope
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what is a store buffer?

can anyone explain what is load buffer and how it's different from invalidation queues. and also difference between store buffers and write combining buffers? The paper by Paul E Mckenny…
harish reddy
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Why use _mm_malloc? (as opposed to _aligned_malloc, alligned_alloc, or posix_memalign)

There are a few options for acquiring an aligned block of memory but they're very similar and the issue mostly boils down to what language standard and platforms you're targeting. C11 void * aligned_alloc (size_t alignment, size_t size) POSIX int…
Praxeolitic
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C code loop performance

I have a multiply-add kernel inside my application and I want to increase its performance. I use an Intel Core i7-960 (3.2 GHz clock) and have already manually implemented the kernel using SSE intrinsics as follows: for(int i=0; i
Ricky
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Intel SSE and AVX Examples and Tutorials

Is there any good C/C++ tutorials or examples for learning Intel SSE and AVX instructions? I found few on Microsoft MSDN and Intel sites, but it would be great to understand it from the basics..
veda
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Intel x86 Opcode Reference?

What is a relatively quick and easy method of looking up what an arbitrary opcode means (say, 0xC8) in x86? The Intel Software Developer's manual isn't very fun to search through...
user541686
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What does Intel mean by "retired"?

In the Intel Manual, there is mention of a lot of performance events which have descriptions like "Mispredicted taken branch instructions retired.". What exactly does retired mean in this context? Note that I have already looked at Intel's…
merlin2011
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Do Intel and AMD processor have the same assembler?

The C language was used to write Unix to achieve portability—the same C language program compiled using different compilers produces different machine instructions. How come the Windows OS is able to run on both Intel and AMD processors?
user136281
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Running Intel® HAXM installer takes forever with Android Studio Setup Wizard on Windows 10

I have a newly installed Android Studio, upon downloading its components I've stuck on the setup wizard Running Intel® HAXM installer: What should I do? Will all my downloaded components lost if I end the task of my Android Studio with my Task…
5ervant - techintel.github.io
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Intel HAXM on macOS high sierra (10.13)

Is there any way of using Android emulator on High Sierra (10.13)? When I run ./HAXM\ installation -u It says: HAXM silent installation only supports macOS from 10.8 to 10.12 !
Andrii Kovalchuk
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Why is Intel Haswell XEON CPU sporadically miscomputing FFTs and ART?

During the last days I observed a behaviour of my new workstation I couldn't explain. Doing some research on this problem, there might be a possible bug in the INTEL Haswell architecture as well as in the current Skylake Generation. Before writing…
semm0
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Does my AMD-based machine use little endian or big endian?

I'm going though a computers system course and I'm trying to establish, for sure, if my AMD based computer is a little-endian machine? I believe it is because it would be Intel-compatible. Specifically, my processor is an AMD 64 Athlon x2. I…
Frank V
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ASM: MASM, NASM, FASM?

I have done ARM assembly programming and I would like to learn the Intel Assembler. I keep hearing all these different F/M/N/ASMs mentioned- but I am unsure how they related to what I wish to achieve? Could somebody please help me identify what I…
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