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Questions tagged [intel]

For issues related to Intel semiconductor chips and assemblies, Intel architectural features and ISA extensions, and Intel chips micro-architecture.

Intel Corporation is an American multinational semiconductor chip maker corporation headquartered in Santa Clara, California, United States. Intel is the inventor of the x86 processor architecture and makes central processing units, motherboard chipsets, graphic processing units, network interface controllers and much more devices related to communications and computing.

In addition to their hardware offerings Intel also produces a variety of software including compilers, libraries for mathematical computation(Intel MKL), threading(OpenMP, Intel Performance Primatives, Threading Building Blocks), parallel communication(MPI,OFED/True Scale Infiniband Stack) and several other products included in the Intel Parallel Studio toolkit. In addition to these offerings which are widely used in HPC Intel also produces software for datacenter management and is one of the most prolific contributors to the Linux kernel.

This tag should be used for questions about Intel hardware and software.

The x86 and/or x86-64 tags are better choices for questions about assembly programming for the architecture, rather than things like performance tuning specifically for Intel's implementation of x86.

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Why does this loop take 1.32 cycles per iteration

Consider this simple C++ function to calculate the prefix sum of an array: void prefix_sum(const uint32_t* input, uint32_t* output, size_t size) { uint32_t total = 0; for (size_t i = 0; i < size; i++) { total += input[i]; …
BeeOnRope
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What are "non-virtualizable" instructions in x86 architecture?

Before the advent of hardware assisted virtualization there were instructions that could not be virtualized due to various reasons. Can somebody please explain what those instructions are and why they cannot be virtualized?
Yadgar Woderf
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How can I find the micro-ops which instructions on Intel's x86 CPUs decode to?

The Intel Optimization Reference, under Section 3.5.1, advises: "Favor single-micro-operation instructions." "Avoid using complex instructions (for example, enter, leave, or loop) that have more than 4 micro-ops and require multiple cycles to…
Alex D
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VirtualBox - Kernel requires an x86-64 cpu but only detected an i686 cpu

Intel i5-2410M CPU running at 2.30 GHz running a Windows 7 64-bit operating system. I have VirtualBox 4.13 installed. I am trying to run ubuntu-14.04-desktop-amd64.iso but I get an error this kernel requires an x86-64 cpu but only detected an i686…
user3861960
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Dynamically determining where a rogue AVX-512 instruction is executing

I have a process running on an Intel machine that supports AVX-512, but this process doesn't directly use any AVX-512 instructions (asm or intrinsics) and is compiled with -mno-avx512f so that the compiler doesn't insert any AVX-512…
BeeOnRope
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What is the stack engine in the Sandybridge microarchitecture?

I am reading http://www.realworldtech.com/sandy-bridge/ and I'm facing some problems in understanding some issues: The dedicated stack pointer tracker is also present in Sandy Bridge and renames the stack pointer, eliminating serial dependencies…
Gilgamesz
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x86-64 canonical address?

During reading of an Intel manual book I came across the following: On processors that support Intel 64 architecture, the IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field must each contain a canonical address. What is a 'canonical address'?
Rouki
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Half-precision floating-point arithmetic on Intel chips

Is it possible to perform half-precision floating-point arithmetic on Intel chips? I know how to load/store/convert half-precision floating-point numbers [1] but I do not know how to add/multiply them without converting to single-precision…
Kadir
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Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures?

I'm doing micro-optimization on a performance critical part of my code and came across the sequence of instructions (in AT&T syntax): add %rax, %rbx mov %rdx, %rax mov %rbx, %rdx I thought I finally had a use case for xchg which would allow me to…
jeteon
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Enabling floating point interrupts on Mac OS X Intel

On Linux, feenableexcept and fedisableexcept can be used to control the generation of SIGFPE interrupts on floating point exceptions. How can I do this on Mac OS X Intel? Inline assembly for enabling floating point interrupts is provided in…
Geoffrey Irving
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Android emulator system images and AMD processor

I use AMD FX X6 6300 type processor. (it supports virtualization and my BIOS setting is ON) I installed "Intel x86 Emulator Accelerator". When I tried to run Intel accelerator setup, I get that setup is unable to install. (error was…
trante
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Size of store buffers on Intel hardware? What exactly is a store buffer?

The Intel optimization manual talks about the number of store buffers that exist in many parts of the processor, but do not seem to talk about the size of the store buffers. Is this public information or is the size of a store buffer kept as a…
Curious
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Which cache mapping technique is used in intel core i7 processor?

I have learned about different cache mapping techniques like direct mapping and fully associative or set associative mapping, and the trade-offs between those. (Wikipedia) But I am curious which one is used in Intel core i7 or AMD processors…
Subhadip
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Why REP LODS AL instruction exists?

In other words, is there any case I might need this instruction? From Intel Instructions Manual, this is what the instruction do: Load (E)CX bytes from DS:[(E)SI] to AL. Take the following example in NASM: section .data src: db 0, 1, 2,…
Bite Bytes
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Why is Skylake so much better than Broadwell-E for single-threaded memory throughput?

We've got a simple memory throughput benchmark. All it does is memcpy repeatedly for a large block of memory. Looking at the results (compiled for 64-bit) on a few different machines, Skylake machines do significantly better than Broadwell-E,…
aggieNick02
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