Questions tagged [instruction-encoding]
99 questions
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x86 ADD instruction 03 prefix?
05 00 00 00 00
is the machine code for one (longer than necessary) encoding of add eax, 0x0
03 05 00 00 00 00
however, is disassembled as add eax, DWORD PTR ds:0x0
from the Intel assembly manual I see that ADD has both op codes for 03 and 05, but I…
cool_cat
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Is there any difference in the multiple encodings of the same x64 instruction?
I am doing some experimentations on x64 assembly instructions, using the Miasm framework. Consider the snippet below, where I disassemble and reassemble the bytecode of LEA RAX, [RIP + 1]:
from miasm.analysis.machine import Machine
machine =…
Katoptriss
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Properly writing a hexadecimal value to an address in x86 machine language
I'm trying to learn how to write x86 machine code as hexadecimal (as part of putting text to the monitor on a qemu cold start.) My guess from reading a few sites was that the proper instruction to write 0x78073807 to 0xB8000 should be something…
Peach
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RISC-V U-Format instruction immediate confusion
Reading the RISC-V unprivileged specification I see that U-format instructions (lui,..) are defined like so:
But the immediate value doesn't make sense to me here: specifically, if given an instruction like lui t0, 0xABCDE, the lower 12 bits of the…
linkedin
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ARMv7 T3 encoding for adds
I can't tell how to determine the following:
i, 10th bit on the left.
imm3, what's the difference for this one with imm8?
Mzq
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Assembly to binary
I am trying to convert lw $t3, 12($t0) to binary but I am stuck.
I am not very familiar with base register addressing. I know that lw is opcode 100011 and that $t3 is rt, and that the 12 represents the 16 bit number. The structure is also:
Opcode =…
user17442276
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Is instruction encoded differently from .so file to runtime memory?
I have an Android .so file that uses ARM-V7A instruction set.
I drag it into IDA, and there is one line that shows :
0x1000: b #0x102c
And the hex window shows that the binary code of b #0x102c is 14 e0.
14 e0 has binary format of 0001 0100 1110…
user16387400
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How does the RMI Instruction Operand Encoding of ROUNDSS work?
A few x86 instructions like ROUNDSS require this seemingly obscure instruction operand encoding, on which I can't find any documentation or definition in Intel's Software Developer's Manual.
How are the bits of this encoding used? I put 66 0f 3a 0b…
soc
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Does offset in ARM Assembly counts from the start or the end?
i am very new to ARM assembly and i want to understand how the actual machine code looks like when you're storing using STUR. To give you an example here's 64 bits
0000 0000 0000 0000 0000
0000 0000 0000 0000 0000
0000 0000 0000 0000 0000
0000
Now…
Areg
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How to determine the values of rs, rd, and rt for MIPS instructions?
For example, the value of rs field for addi $t1, $t2, 20 is 01010. Why is that?
Heavenguard.01
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Instruction Encoding?
My professor wanted to show us how to decode instructions, as an example he took (at&t syntax):
movq $8, 4(%rdx,%rsi,4)
I'm quit lost on why he chose the opcode to be C7.
From an online table I found:
C7- move imm32 to r/m32 or imm32 (sign extended…
algo
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What's the difference between the 2 groups of instructions given below regarding the non-use of the prefixes 66/F2/F3?
Section 3.1.1.1 on Chapter 3 of Volume 2 of Intel's documents says the following regarding NP:
NP — Indicates the use of 66/F2/F3 prefixes (beyond those already part of the instructions opcode) are not allowed with the instruction.
Such use will…
Belloc
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Target destination of a JE branch instruction, given its machine code and starting address
I'm reading the textbook Randal E. Bryant, David R. O’Hallaron - Computer Systems. A Programmer’s Perspective [3rd ed.] (2016, Pearson)
I came across this question and I am not sure how the authors obtained the answer.
In the following excerpts from…
Megan Darcy
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Encoding 8-bit operand size? Is there a prefix for that like for 16-bit?
In instruction encoding Default sizes are:
operand size is 32 bit
address size is 64 bit
We can use the legacy prefix:
0x66 – Operand-size override prefix
to make operand size 16. What if I want to make it 8 bits not 16?
user16566250
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Why is multiplication by 4 needed to offset when you calculate branch target address?
I understand when I translate C code into MIPS language, the address needs to be multiplied by 4.
i.e ) int x = A[1] => lw $t1, 4*1 (address of A)
But I don't know why it is also the case for branch target address.
From this Q&A How to Calculate…
Js Park
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