Questions tagged [instruction-encoding]
99 questions
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how arm-thumb instruction set's blx instruction support 4MB range
Read from https://www.keil.com/support/man/docs/armasm/armasm_dom1361289866046.htm that arm-thumb instruction's blx instruction can support maximum 4MB of jump range.
But as far as I know, arm-thumb instruction is only 16 bits long, so how can 16…
user16387400
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ModRM: Can't use direct address, assembly x86
I can't understand why I receive an Illegal Instruction with a piece of code implemented as assembly inside C program. I explain a bit.
I have a value at a specific address and I want to move that value into EAX x86 register, something like
MOV EAX,…
Francesco
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mips type R, I and J, RS, RT and RD fields length
Is there any particular reason why RS, RT and RD fields have 5 bits?
leandro koiti
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What does "input size" mean in "Compressed Displacement (disp8*N) Support in EVEX"?
In Intel(R) 64 and IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Order Number: 325462-080US June 2023.
2.7.5 Compressed Displacement (disp8*N) Support in EVEX
For memory…
YutakaAoki
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Why does the opcode for MOV from a segment register not have its low bit set? It's not 8-bit operand-size, so the W bit should be set
I am having a problem where I can't understand the opcode of this instruction MOV BX,CS like the first byte is 10001100 where the first 6 bit represents the opcode then the direction 1 bit follows then the W. So here is my doubt why in the opcode it…
SmilyFace
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Opcode differences between MOV r/m32, imm32 and MOV r32, imm32
These are MOV instruction opcodes from the Intel® 64 and IA-32 Architectures Software Developer Manuals:
B8+ rd id MOV r32, imm32 OI Valid Valid Move imm32 to r32.
C7 /0 id MOV r/m32, imm32 MI Valid Valid Move imm32 to r/m32.
I disassembled as…
UPinar
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Assembly mov pointer calculation? How does it?
00007FF6FB15A7C0 | 48:8B05 594C6700 | mov rax,qword ptr ds:[7FF6FB7CF420]
So how does computer calculate this 7FF6FB7CF420? I want to get data myself from there so I need a pointer.
Something to do with those bytes? Adding them to Exe…
ayes l
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What is SignImm in Branch Target Address formula context? (BTA)
I would like to know what is SignImm in the following formula:
BTA = Branch Target Address = PC(old) + 4 + (SignImm << 2)
I have read that it is the address distance between the old PC + 4 and the new target address, but I have not seen it in a…
Lechius
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ARMv7E-M VCVT.F32.U32 encoding
I'm writing an ARMv7E-M Thumb2 binary analysis tool, and decoding the instruction stream manually.
arm-gcc, invoked with the -mcpu=cortex-m4 and -mfloat-abi=hard flags, emitted the following instruction while compiling my C code:
40280: eeb8 7a47 …
Charles Nicholson
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8086 instruction set: MODR/M byte
The 8086 documentation sites seem a bit vague when the MODR/M byte is mentioned and it's really difficult to comprehend what it is and does.
What are all the bits used for in the MODR/M byte and what are the possible options?
Some documentation I've…
Mauser_Maschine
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Deciphering an SIB encoding from Intel x86-64
Here's a simple hello world file
#include
int main() {
printf("hello, world\n");
return 0;
}
Here is the instruction to load the address of a string from the .rodata section into a register
lea rax,…
Happy Jerry
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Intel Reference Specification Questions
I'm looking at the ADD instruction, and there are so many things I don't have an idea what they mean.
The gaps I have are.
In the Opcode column what is /0 and /r?
I understand the number is the opcode in hex. The ib/iw/id is byte/word/doubleword.…
christopher clark
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Force NASM to use quadwords
In gas, I can do movabs rcx, 0x402041, which assembles to 48b941204000. NASM doesn't support movabs. I've tried doing mov rcx, 0x402041, and mov rcx, QWORD 0x402041, but, in either case, NASM assembles it to b941204000 which disassembles to mov…
SRobertJames
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Are more byte sequences valid than not when interpreted by an x86 CPU?
This might seem an odd question, but I think it's relevant to certain x86 binary analysis hurdles. I'm pondering this idea: If I have a binary which reaches out to a remote server for a jump destination, but the server won't tell me the destination…
J.Todd
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How do hardware recognizes RISC-V compressed instructions?
It's my first time to ask questions on stackoverflow and I have done some searching about this question. And if there is something I missed, please let me know.
I want to ask how do hardware recognize RVC instructions.
For example, I fetch a 32-bit…
孙志博
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