Questions tagged [fsm]

Acronym for Finite State Machine.

Finite state machine, finite state automata, or state machine, is used in computer science or logic theory to represent a finite number of states and the transitions between states.

Finite state machines are commonly used in parsing and matching strings, so it accepts certain types of strings (such as those representing an integer), and a language (set of strings) is regular if and only if it can be represented as a finite state machine.

An example of a finite state machine implementation in pseudocode, accepting all decimal integers:

state = 0;
digits = "152341264"; // Some sequence of decimal digits
for (k = 0; k < len(digits); k++) {
    switch (state) {
    case 0: // Initial state
        if (digits[k] is a decimal digit)
            state = 1;
        else
            state = 2;
        break;
    case 1: // Digit found, also an accepting state
        if (digits[k] is a decimal digit)
            state = 1;
        else
            state = 2;
        break;
    case 2: // Dead state
        break;
    }
}
FSM accepts the string digits if it finishes at state 1.

Finite state machines represent all the regular languages, or Type 3 languages, which are the lowest in the Chomsky hierarchy, below the context-free (Type 2) languages, which is below the context-sensitive (Type 1) languages, which is below the recursively enumerable (Type 0) languages.

Wikipedia page

The tag is also known like on stackoverflow.

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FSM in vhdl using counter as output

I am currently writing my first FSM and am unsure of if I have the logic correct. I am tasked with creating a state diagram for the following logic: A = 00 B = 01 C = 10 D = 11 Output is 1 when: BDA BAA BAD So I created the following vhdl code to…
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Only one gameobject being affected by script

Making a state machine AI "game" I have 3 states Movement, Combat, and View. They all work very well, now I'm making a flee (by the way if anyone has any good links to tutorials or info that they have off hand I would love that) state so I want to…
user2344665
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How to only affect 1 gameobject in an if statement

Making an AI game, trying to only affect 1 gameobject in an if statement. I think the way I'm doing it is very wrong, and I was advised to create an array of my instance of my enum. I'm just not sure the best way to go about this. This is the code I…
user2344665
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What are steps for generating fsm code in C or C++ with NunniFsm?

I have seen that,there is free source fsm generator named NunniFsm .For that you can refer http://www.nunnisoft.ch/nunnifsmgen/en/home.jsp .I have downloaded the source package and examples.The readme explain the steps to create fsm for java…
Sarfraj
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My speed goes down, what am I missing?

I have designed 2 FSMs for CRC purposes. I got the base code (xor tree) from an online CRC generator, and build around it the FSMs, one for Tx and one for Rx. It works great. When I test either, ON ITS OWN, i get 200+ MHz speed. When I try to test…
sparkyT
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FSM for email address format validation

Have come up with the following Finite State Machine for validating an email based on the following pattern. Is this valid to be able to validate an emailaddress format (more specifically, is the FSM a correct translation of the regex…
iCrus
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write FSM for for loop in verilog

I want to implement this for loop through a FSM int j; for(int i=0;i<50;i++) { j++ } I think 3 states are required: init, increment and done. init -> initialization increment -> will increment i/j done -> final state my try module…
Sangeet Saha
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VHDL - FSM Control

I'm a beginner and I need a little help . My "current_s" is changing whenever rising edge of the clock detected. But, I want it to change only once when "Dot" or "Dash" is '1'. I tried to create a signal like: Go_s<=Dot or Dash; And then tried to…
massakrienen
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Akka FSM vs Storm for media content rendering application

I have actor system with data flow route depending on passed data. Now I want to extract common pieces of code from actors and introduce states. Like if I want to build video with audio - then either on "ffmpeg" state I have to wait for both…
jdevelop
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simulating centipede finite state machine

I'm trying to write a centipede game clone, and I have written a node class which is basically a circle. I'm trying to write an FSM to simulate node movements and bouncing with bricks or the screen, but the problem, that the FSM conflicts with…
Andre
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ISSUE: Error (10818): Can't infer register for "y[0]" at FSM_LCD.vhd(42) because it does not hold its value outside the clock edge

I'm trying to implement a finite state machine that has a delay(500ns) between each state transition with a 50Mhz clock, so 25 clock cycles delay. Notice that: EA=current state PE=next state reset "resets" when 0 I was making a count from y=0 to…
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Type conversion - string of characters to integer

Hello I am writing my program in C, using PSoC tools to program my Cypress development kit. I am facing an issue regarding type conversion of a string of characters collected in my circular buffer (buffer) to a local variable "input_R", ultimately…
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How to solve a combinatorial logic with an output feeding back to the input, forming a loop?

I have this warnig in my code for a FSM: WARNING:Xst:2170 - Unit P22_MustangSecuentialTailLight_Structural : the following signal(s) form a combinatorial loop: Lights<5>, U1/next_state_cmp_eq0000, next_state_int<0>,…
Mac
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VHDL sequencer: incrementing output sigals in FSM

I am working on a Sequencer and I can not figure out how to increment some output signals. In state 1 (S1) I want to increment the ram_add_wr (on every clock cycle). clocked_process:PROCESS(clk,rst) VARIABLE count: INTEGER RANGE 0 TO 32; BEGIN …
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Why does this Ragel file generate implicit conversion errors? (Ragel with D)

I have the following (very simple) Ragel file scanner.rl: void lex(string data) { int cs, act, top; auto p = data.ptr; typeof(p) pe = &data[$ -1], eof = pe, ts, te; %%{ machine scanner; …
Jordan
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