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Questions tagged [bus]

A Bus is a physical device used to connect different functional blocks of a computer or a different computers in order to communicate them together. Also Bus is a data type in MATLAB language used to bundle some data to virtual (just for useful rendering) or non-virtual (for contiguous memory allocation) structure.

The Bus advantages (as physical device) over wires are reducing the needed number of wires and catholicity. The main characteristics of Buses are width (amount of bits can be transmitted at once) and frequency (work speed).

The Bus as a structure of MATLAB language used to bundle different variables (or signals, for example in Simulink) in one structure. Can be used as virtual bus just for convenient accessing to variables and for reducing number of wires at Simulink diagram or as non-virtual - Nonvirtual buses use contiguous memory allocation for variables.

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How can 8086 processors access harddrives larger than 1 MB?

How can 8086 processors (or real mode on later processors) access harddrives larger than 1 MB, when they can only access 1 MB (without expanded memory) of RAM?
Alpha_Pi
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How to run Rebus endpoint with a generic host

I have implemented a Rebus endpoint as a service following this post (How to configure a Rebus endpoint to run as a service) but I'm wondering if there is a generic host application for Rebus like other bus services like NServiceBus, MassTransit,…
foxhard
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How to catch Exception in split-join catchAll on OSB?

I want to catch exception in split join but the fault variable is empty and it is not showing any exception . Kindly give me any solution so I can catch and log it. Regards, Junaid
Ahmed Junaid
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Load balancing not working OSB

I am trying to understand the Oracle Service Bus Load Balancing. I have: One weblogic server 10.3.6.0, with 3 Managed servers (lb,osb1,osb2): 2 Managed servers are in cluster configuration: osb1 - with port 7101 and osb2 - with port 7202 The…
José Ch
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Is it ok to use Otto outside android?

I am working on a Java EE project that constantly talks to a webservice, I have some experience using Otto on Android and I was wondering if would be ok if I add it to this project too. What you say?
Marcos J.C Kichel
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Is there a vendor independent AXI4 (Lite) builder for FPGAs

I am wondering if anyone know of a good vendor independent AXI4 (Lite/Stream) interconnect constructor like Qsys or IP configurator. I would prefer to build an FPGA system platform that is as vendor independent as possible.
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Simulink: individual signal output from bus input (based on signal name)

I have a complex Simulink model and want to generate in a subsystem one simple error message signal out of a lot of incoming error observing signals. These incoming signals are organised in a bus and are always 0, exept when an error occurs: then…
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Connect Azure Pack to Service Bus for Windows Server with Custom DNS

I'm trying to configure Azure Pack to use Service Bus for Windows Server 1.1 with Custom DNS. All runs on one virtual machine (Windows Server 2012 R2) in Windows Azure. I following this…
Zanael
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Pause the worker from getting messages from the queue

I have been to trying find out if there is any way to pause the worker from taking more jobs/messages from the Rebus queue? I want to be able to "disable" a worker through my GUI so that it finishes the job its currently working on (if any) and then…
jopa
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Rebus and Handlers with Expensive Initialization/creation

As far as I know the usual behavior of buses including Rebus is creating a new handler for each message that arrives and match. This is fine in most cases but sometimes there will be expensive initialization handlers (will require to instantiate…
Jhonatan P
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how to configure cxf bus to specify servlet context (the /cxf part)?

Up until now I have been using apache cxf to host some web services, and my bus is configured in blueprint.xml like so: The web application is available on…
vikingsteve
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MATLAB/SIMULINK dynamic bus conversion with embedded Matlab function

I'm working on automated model building. In some cases I have do convert a bus into another bus (the structure is the same, but there can be variants in the names). It works for a static model where I can change the datatype of the inputs and…
Basti
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how wide are 32 and 64 bit architecture buses?

I was reading my Systems Programming book and got to a chapter about Hardware organisation of Systems. This was first time me reading about Hardware organisation of Systems so I got really interested and try to understand as much as possible. This…
GreedyAi
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Bus Error Upon Calling Delete (C++)

I've been creating a class that takes a bunch of images and overlays them onto one BMP. For some reason upon running the code I'm getting a segfault and I've tracked it down to this method. Essentially the if statement checks to see if there is a…
Arjun Nayini
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How to designate port as byte array in VHDL

Alright guys, sorry if this is a question that's been asked already, as I'm new enough to VHDL logic design to not know exactly how to term a particular concept. What I'm trying to do is implement the AES-256 algorithm in VHDL for FPGA use. I have a…
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