Is there a vendor independent AXI4 (Lite) builder for FPGAs

Question

I am wondering if anyone know of a good vendor independent AXI4 (Lite/Stream) interconnect constructor like Qsys or IP configurator.

I would prefer to build an FPGA system platform that is as vendor independent as possible.

Answer 1

You can use AXI template procedures implemented in the following repository (VHDL, BSD license): https://github.com/sergeykhbr/riscv_vhdl

File types_nasti.vhd implements registers bank specific for the AXI bus, general update procedure and access functions that should be called from user's device.

The project structure is very similar to Gailser's LEON3 implementation but it implements 64-bits Rocket-Chip CPU (RISC-V ISA) and several AXI4 modules: UART, GPIO, IRQ controller etc. They could be used as an examples of using AXI template procedures.