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I noticed that Verilog rounds my real number results into integer results. For example when I look at simulator, it shows the result of 17/2 as 9. What should I do? Is there anyway to define something like a: output real reg [11:0] output_value ? Or is it something that has to be done by simulator settings?

Simulation only (no synthesis). Example:
x defined as a signed input and output_value defined as output reg.

output_value = ((x >>> 1) + x) + 5;

If x=+1 then output value has to be: 13/2=6.5.

However when I simulate I see output_value = 6.

Morgan
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Amadeus
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1 Answers1

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Code would help, but I suspect your not dividing reals at all. 17 and 2 are integers, and so a simple statement like that will do integer division.

17   / 2   = 8 (not 9, always rounds towards 0)
17.0 / 2.0 = 8.5

In your second case

output_value = ((x >>> 1) + x) + 5

If x is 1, x >>> 1 is 0, not 0.5 because you've just gone off the bottom of the word.

output_value = ((1 >>> 1) + 1) + 5 = 0 + 1 + 5 = 6

There's nothing special about verilog here. This is true for the majority of languages.

Paul S
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  • I understand.. Thank you for your explanation. Now, I am wondering how can I get the result as 6.5 while calculating output_value = ((x >>> 1) + x) + 5 at x=1. I tried to adjust x=1.0 at testbench. However it did not solve my problem. Is there a way to define x input as a real number? – Amadeus Mar 17 '12 at 19:20