Rounding off a number in verilog

Question

Basically I'm trying to code a synthesizable module in verilog which performs division between 2 numbers and rounds off the result . For example, if I'm doing 56/30 then resulting value is 1.86 and this value should be rounded off to 2 or if I'm doing 42/30 , the resulting value is 1.4 which should be rounded off to 1 . Can synthesizable code be written in verilog to achieve this?

You need to give more detail. Which synthesiser have you got? Most will only turn the '/' operator into a divider if it's actually just a shifter - the divisor must be a constant power of two. What are your number formats? Do you understand rounding? You probably need to code a divider - look up 'non restoring division'. — EML, Sep 27 '13 at 07:52
Basically the numbers which I'm using for calculations are inputs to my module. So the numbers are in wire format. You mentioned that divisor must be a constant power of two . But during simulation , I got the output of the 56/30 as 1 which is the floor value of the quotient . My doubt is , can the code be synthesized if the divisor is a number other than power of 2 ? — Sharath Bhat, Oct 02 '13 at 15:29
I believe @EML was referring to the fact that if a constant or selection of divisors (denominators) were defined as powers of 2 you would get a shifter rather than a divider. A shifter being very area and power efficient in comparison to a divider. — Morgan, Oct 02 '13 at 16:28

score 1 · Answer 1 · edited May 23 '17 at 12:31

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Verilog truncates the end of a number if <size> is smaller than the value returned. So if you divide 42/30, the value returned is 1.4. Simply define the <size> as 1, and the decimal will be truncated.

However, keep in mind that this solution truncates the decimal, and doesn't round it up. I'm not an expert at Verilog, but you could refer here to further solve your problem.

edited May 23 '17 at 12:31

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answered Sep 23 '13 at 10:17

Vedant Chandra

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Morgan · Accepted Answer · 2013-09-23T12:32:37.113

The value of the answers LSB is determined by the input format. If you change the numerator input to Fixed point with at least 1 Fractional bit rather than integers, your output will have a bit representing 0.5 which you can use to control truncate (round down) or round up.

module test;

reg[4:0] a = 5'b0011_0; //3 with 1 Fractional bit
reg[4:0] b = 5'b00010;  //2 no fractional bits
reg[9:0] c;

initial begin
  c = a/b ; //LSB => 0.5
  // c= 5'b01_1 => 1.5
  #1 $display("C = %b", c);
end
endmodule

Rounding off a number in verilog

2 Answers2