How to access the members of a struct in SystemVerilog from C++ testbench?

Question

I have a SystemVerilog hardware design, in which there is such a struct below (no need to care about what they exactly are, just an example here):

typedef struct packed {
    logic [riscv::VLEN-1:0]   pc;            
    logic [TRANS_ID_BITS-1:0] trans_id;     
    fu_t                      fu;            
    fu_op                     op;           
    logic [REG_ADDR_SIZE-1:0] rs1;           
    logic [REG_ADDR_SIZE-1:0] rs2;           
    logic [REG_ADDR_SIZE-1:0] rd;           
    riscv::xlen_t             result;        
    logic                     valid;         
    logic                     use_imm;      
    logic                     use_zimm;
    logic                     use_pc;       
    exception_t               ex;            
    branchpredict_sbe_t       bp;           
    logic                     is_compressed; 
} scoreboard_entry_t;

The testbench used to simulate this design is written in C++ and the simulator is Verilator. It is already clear that Verilator does NOT support accessing the members in this struct via VPI interface. Is there any other way around to access an individual memebr in this struct from its C++ testbench?