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I'm trying to simulate my VHDL component in Vivado and i'm receiving a compilation error: "formal generic 'n' has no actual or default value". I would appreciate any advice or solution to this error.

I have seen the issue VHDL: formal port 'portName' has no actual or default value and my error, although similar, does not seem related.

entity bit_tester is 
generic (N : integer);
port(in1 : in bit_vector (N-1 downto 0);
    out1 : out bit;
    out2 :out bit;
    out3 :out bit);
end bit_tester;

architecture behavioral of bit_tester is
DeReK YuEn
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    *...and my error, although similar, does not seem related.* Prithee how does your error differ that's it not related? See [ask], provide a [mcve]. A generic constant either has an assigned value (in a generic map), has a default value or produces an error. Some simulators can supply generics values as command line arguments. – user16145658 Sep 19 '22 at 04:20
  • You need to show the relevant code. In this case it is also the instance of entity bit_tester. At that point, you did not give the generic a value. Do a google search on mapping VHDL generics. – Jim Lewis Sep 20 '22 at 02:47

1 Answers1

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It's not clear from the question how you are trying to simulate this entity.

But you are not providing a value for your generic "N"

You have to either assign it a default value:

entity bit_tester is 
generic (N : integer := 5);
port(in1 : in bit_vector (N-1 downto 0);
    out1 : out bit;
    out2 :out bit;
    out3 :out bit);
end bit_tester;

Or give it a value when you instantiate the entity:

inst_bit_tester:bit_tester
generic map(N => 5)
port map(in1 => in1,
    out1 => out1,
    out2 => out2,
    out3 => out3);
expuexto
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