Instantiate VHDL entity with 2D array from SystemVerilog

Question

There seems to be very little documentation on how to pass 2D arrays between VHDL and SystemVerilog. I have a port of the following type in VHDL:

package my_package is
    type my_array_t is array (natural range <>) of std_logic_vector(N-1 downto 0);
end my_package

entity my_entity is
    port(
        my_input  : in  my_array_t(M-1 downto 0);
        my_output : out my_array_t(M-1 downto 0);
    );
end entity;

And the following SystemVerilog signal:

wire [N-1:0] my_input_s[M-1:0];
wire [N-1:0] my_output_s[M-1:0];

I believe these two types are completely equivalent. However, I can't go between each other without getting errors. Instantiating the VHDL module from SystemVerilog:

my_entity my_entity_inst(
    .my_input(my_input_s),
    .my_output(my_output_s)
);

The error I get is "formal port 'my_input' of type 'my_array_t' does not match with actual type 'logic'", similarly for the output signal. I tried different combination of array types in SystemVerilog (fully packed, fully unpacked) but none works. Note that in my case, I don't have the freedom of changing the VHDL declaration, I must find a way to make it work solely from SystemVerilog. Thus, this question can't help me.

How do I instantiate my VHDL module from SystemVerilog in the most straightforward way?

Mikef · Accepted Answer · 2022-05-20T15:38:59.853

0

To be successful in instantiating VHDL in Verilog or SV stick to the basic types (types built into the original VHDL, not custom packages) in VHDL such as std_logic and std_logic vector.

For this case where you can't modify the VHDL file with custom port types, I recommend writing a VHDL wrapper (mydesign_wrapper.vhd) that instantiates the entity which uses the custom types and converts the ports to std_logic and std_logic_vector types for use at the top/entity of the wrapper design. Instantiate the new wrapper file in the Verilog or SystemVerilog file. An array of std_logic_vector would be represented as several std_logic_vector ports using the wrapper.

There is no standard for VHDL inside Verilog/SV, therefore support is limited and varies between tools, vendors, and versions.

edited May 20 '22 at 15:38

answered May 20 '22 at 15:01

Mikef

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To further minimize anything that could go wrong: 1) Hard code VHDL generics in the wrapper so that they are not exposed to SystemVerilog. 2) Take care that the order of ports listed on the SystemVerilog instance is the same order as they are defined on the VHDL entity. 3) Verify the approach works for simulation and syntheses flows early. Dry-run the approach on a very very small test design first before modifying and verifying a lot of code and getting it to work in simulation. Don't want to make it beautiful fancy in simulation to find out it does not even build in synthesis. – Mikef May 20 '22 at 16:37

Instantiate VHDL entity with 2D array from SystemVerilog

1 Answers1