Connecting multidimensional systemverilog port to vhdl module

Question

I am trying to instantiate a systemverilog module inside a vhdl top module. The systemverilog module uses a 2-dimensional packed array "channel_addr_i"(A packed array of 3 addresses each consists of 3 bits)

SystemVerilog module declaration:

`define N_PORTS 3
`define N_CHANNELS 4 

 module pwr_ctrl(
            input   logic                clk, rst_n,     
            input   logic [`N_PORTS-1 : 0] [2 : 0]   channel_addr_i,
            input   logic [`N_CHANNELS-1  : 0]   transaction_complete_i,
            output  logic [`N_CHANNELS-1  : 0]       sleep
    );

---

I have to instantiate the above module as a component in the top level vhdl module and pass the addresses from 3 different input ports(each address consists of 3 bits: so in total 9 bits) to the systemverilog component.

VHDL Instantiation:

 signal ch_addr    : std_logic_vector(8 downto 0);

 component pwr_ctrl is
port(

  clk   : in std_logic;
  rst_n : in std_logic;

  channel_addr_i            : in  std_logic_vector(8 downto 0); --CONSIDERING 3 INPUT PORTS
  transaction_complete_i    : in  std_logic_vector(3 downto 0); -- CONSIDERING 4 CHANNELS    
  sleep                     : out std_logic_vector(3 downto 0)

  );

 ch_addr  <= axi_addr(31 downto 29) & axi1_addr_n(31 downto 29) & addr_ahb(31 downto 29);


  power_ctrl : pwr_ctrl
port map(

  clk           => aclk,
  rst_n         => aresetn,

  channel_addr_i          => ch_addr,
  transaction_complete_i  => transaction_complete_i,
  sleep                   => sleep

);
end component; 

But modelsim gives this error: ** Error: (vsim-8428) Cannot connect a VHDL array signal to Verilog multi dimensional array port 'channel_addr_i'.

Can anybody suggest another alternative other than changing the port type in systemverilog module?

Answer 1

My thanks to Martin with his comment. Your problem can be solved by using:

type two_dim_array is array (natural range <>, natural range <>) of std_logic;

I declared and assigned successfully. Sorry about my stupid answer :(

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OLD ANSWER

I don't think System-verilog is compatible with VHDL in this case because old VHDL NOT REALLY support multidimensional array. But, you should try this one (I've not yet tried it because our lab use very old modelsim):

Change your setting to VHDL 2008 then you can declare type

type two_dim_array is array (natural range <>) of std_logic_vector;

Then try it again.

But, best case is expand your system-verilog to wrapper with expanded array.

P/S: At last time I tried with system-verilog project, the multi-dimensonal array is automatic expanded in synthesis tool to 1-dimensional array. However, simulation tool may not allow it. Goodluck!