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There is a testbench env and I am working on some tests, I noticed that in the waveform if I pull a specific signal which is input to rtl from rtl hierarchy and pull the same signal from the driver clocking block, I see that the signal at rtl hierarchy is one clock delayed as compared to the same signal at the driving clocking block hierarchy while if I pull out a signal in waveform which is output from rtl at rtl hierarchy and the same signal at the monitor clocking block hierarchy, I see the same signal at monitor clocking block level is delayed by one cycle.

Are the signals at monitor clocking block level always delayed and at driver clocking block level always come one clock early with respect to the signals seen at rtl hierarchy?

The prototype of interface is like this :

          interface my_if(input bit clk, bit reset);
             bit valid;
             bit [31:0] data;
             bit [2:0]  crdt; 

 
              clocking monitor_cb @(posedge clk); 
              default input #1 output #1; 
              input valid; 
              input data;
              input crdt;
              endclocking 

              clocking tx_driver_cb @(posedge clk); 
              default input #1 output #1; 
              output valid; 
              output data;
              input crdt;
              endclocking 

              clocking rx_driver_cb @(posedge clk); 
              default input #1 output #1; 
              input valid; 
              input data;
              output crdt;
              endclocking 
   
           modport tx_driver (clocking tx_driverv_cb);
           modport rx_driver (clocking rx_driver_cb);   
           modport monitor (clocking monitor_cb);

         endinterface
Bob
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Grace90
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1 Answers1

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Let's take the monitor_cb.data as an example for the input case

The inputs will be delayed #1 will be sampled at the rising edge of clk.

// (pseudo code)
logic [31:0] skew_data;
assign #10 skew_data = my_if.data;
always @(posedge clk) begin
  monitor_cb.data <= skew_data;
end

If your signal changes at the rising edge of the clock, the sampled_data will hold the value before the update.

Now for the outputs what is delayed is the sampling moment not the signal

always @(posedge clk) begin
  #1;
  tx_driver_cb.data <= data;
end

The data is sampled slightly after the clock, so it samples the updated value.

Bob
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